From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Thu, 19 Feb 2015 20:25:14 +0000 (-0800)
Subject: Unify rv32/rv64 timer tests
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e0532426bcd8634041be23457ff78a90e78db466;p=riscv-tests.git

Unify rv32/rv64 timer tests
---

diff --git a/isa/rv32si/timer.S b/isa/rv32si/timer.S
index 0e3a623..5c627d5 100644
--- a/isa/rv32si/timer.S
+++ b/isa/rv32si/timer.S
@@ -10,42 +10,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
 
-  la t0, evec
-  csrw evec, t0
-
-  csrr t0, count
-  add t0, t0, 1000
-  csrw compare, t0
-
-  li t1, 1<<23
-  csrs status, t1 # turn on timer IRQ 7
-  csrsi status, 4 # enable interrupts
-
-  li TESTNUM, 2
-  li a0,10000
-loop:
-  div x0, x0, x0
-  addi a0, a0, -1
-  bne a0, x0, loop
-  j fail # assumption is that you can't divide in one cycle
-
-  TEST_PASSFAIL
-
-evec:
-  li TESTNUM, 3
-  li t1, 0x80000000|IRQ_TIMER
-  csrr t0, cause
-  bne t0, t1, fail
-  j pass
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
+#include "../rv64si/timer.S"
diff --git a/isa/rv64si/timer.S b/isa/rv64si/timer.S
index 80b22e9..0a90a60 100644
--- a/isa/rv64si/timer.S
+++ b/isa/rv64si/timer.S
@@ -32,8 +32,7 @@ RVTEST_CODE_BEGIN
   srl s0,s0,1
   sll s2,s2,9
   or  s0,s2,s0
-  sll s0,s0,54
-  srl s0,s0,54
+  and s0, s0, 0x3FF
   add s4, s4, 1
   bltu s8, s9, 1b
 
@@ -54,10 +53,13 @@ RVTEST_CODE_BEGIN
   TEST_PASSFAIL
 
 handler:
-  csrr t0, cause
-  li t1, 0x8000000000000007
   li TESTNUM, 3
-  bne t0, t1, fail
+  csrr t0, cause
+  bgez t0, fail
+
+  sll t0, t0, 1
+  addi t0, t0, -2*IRQ_TIMER
+  bnez t0, fail
 
   csrr t0, count
   addi t0, t0, 999