From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 27 Aug 2007 03:25:42 +0000 (-0700)
Subject: Simple CPU: Make sure only instructions which complete without faulting are counted.
X-Git-Tag: m5_2.0_beta4~177
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e056e49c4562108eeb7abbbeb1ee8acb096fe363;p=gem5.git

Simple CPU: Make sure only instructions which complete without faulting are counted.

--HG--
extra : convert_revision : 01019c7129ed762d8826c3e6519989aa3fc3b5fd
---

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 379c50b51..86deb84e6 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -546,6 +546,11 @@ AtomicSimpleCPU::tick()
             if(curStaticInst)
             {
                 fault = curStaticInst->execute(this, traceData);
+
+                // keep an instruction count
+                if (fault == NoFault)
+                    countInst();
+
                 postExecute();
             }
 
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index aabaf1971..d6b124efc 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -357,12 +357,6 @@ BaseSimpleCPU::preExecute()
     thread->setFloatReg(ZeroReg, 0.0);
 #endif // ALPHA_ISA
 
-    // keep an instruction count
-    numInst++;
-    numInsts++;
-
-    thread->funcExeInst++;
-
     // check for instruction-count-based events
     comInstEventQueue[0]->serviceEvents(numInst);
 
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 843fd025c..2bc329b68 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -157,6 +157,14 @@ class BaseSimpleCPU : public BaseCPU
     Counter startNumInst;
     Stats::Scalar<> numInsts;
 
+    void countInst()
+    {
+        numInst++;
+        numInsts++;
+
+        thread->funcExeInst++;
+    }
+
     virtual Counter totalInstructions() const
     {
         return numInst - startNumInst;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 70b774deb..046b2fe3b 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -540,13 +540,23 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
                 delete dcache_pkt->req;
                 delete dcache_pkt;
                 dcache_pkt = NULL;
+
+                // keep an instruction count
+                if (fault == NoFault)
+                    countInst();
             }
+
             postExecute();
             advanceInst(fault);
         }
     } else {
         // non-memory instruction: execute completely now
         Fault fault = curStaticInst->execute(this, traceData);
+
+        // keep an instruction count
+        if (fault == NoFault)
+            countInst();
+
         postExecute();
         advanceInst(fault);
     }
@@ -615,6 +625,10 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
 
     Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
 
+    // keep an instruction count
+    if (fault == NoFault)
+        countInst();
+
     if (pkt->isRead() && pkt->isLocked()) {
         TheISA::handleLockedRead(thread, pkt->req);
     }