From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 23 Sep 2021 14:05:12 +0000 (+0100)
Subject: add load-immediate unit test
X-Git-Tag: sv_maxu_works-initial~844
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e0641eb5dea0ba6c5cc7f196201edd040f99c52a;p=openpower-isa.git

add load-immediate unit test
---

diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index 6dc4fd90..f5789d86 100644
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -38,6 +38,22 @@ class DecoderTestCase(FHDLTestCase):
             print("FPR 1", sim.fpr(1))
             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
 
+    def test_fpload_imm(self):
+        """>>> lst = ["lfs 1, 8(1)",
+                     ]
+        """
+        lst = ["lfs 1, 8(1)",
+                     ]
+        initial_mem = {0x0000: (0x42013333, 8),
+                       0x0008: (0x42026666, 8),
+                       0x0020: (0x1828384822324252, 8),
+                        }
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_mem=initial_mem)
+            print("FPR 1", sim.fpr(1))
+            self.assertEqual(sim.fpr(1), SelectableInt(0x40404cccc0000000, 64))
+
     def test_fpload2(self):
         """>>> lst = ["lfsx 1, 0, 0",
                      ]