From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 2 Sep 2020 17:48:34 +0000 (+0100)
Subject: fix bug in cmpli (and cmplw)
X-Git-Tag: semi_working_ecp5~211
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e06496e7d1af3227a6f3d24166058bd728ff64a9;p=soc.git

fix bug in cmpli (and cmplw)
---

diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py
index 7f98c344..b4c4bb2a 100644
--- a/src/soc/fu/alu/main_stage.py
+++ b/src/soc/fu/alu/main_stage.py
@@ -60,7 +60,10 @@ class ALUMainStage(PipeModBase):
 
         a_i = Signal.like(a)
         b_i = Signal.like(b)
-        with m.If(is_32bit):
+        with m.If(op.insn_type == MicrOp.OP_CMP): # another temporary hack
+            comb += a_i.eq(a)                     # reaaaally need to move CMP
+            comb += b_i.eq(b)                     # into trap pipeline
+        with m.Elif(is_32bit):
             with m.If(op.is_signed):
                 comb += a_i.eq(exts(a, 32, 64))
                 comb += b_i.eq(exts(b, 32, 64))
diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 5d8122c7..5cf37307 100644
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -288,6 +288,25 @@ class ALUTestCase(TestAccumulatorBase):
                                 initial_sprs = {'XER': XER},
                                 initial_cr = CR)
 
+    def case_cmpli_microwatt(self):
+        """microwatt 1.bin: cmpli
+           123ac:   9c 79 8d 2a     cmpli   cr5,0,r13,31132
+            gpr: 00000000301fc7a7 <- r13
+            cr : 0000000090215393
+            xer: so 1 ca 0 32 0 ov 0 32 0
+
+        """
+
+        lst = ["cmpli 5, 0, 13, 31132"]
+        initial_regs = [0] * 32
+        initial_regs[13] = 0x301fc7a7
+        XER = 0xe00c0000
+        CR = 0x90215393
+
+        self.add_case(Program(lst, bigendian), initial_regs,
+                                initial_sprs = {'XER': XER},
+                                initial_cr = CR)
+
     def case_extsb(self):
         insns = ["extsb", "extsh", "extsw"]
         for i in range(10):
diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 13e41029..afe4140f 100755
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -308,7 +308,7 @@ class LibreSoCSim(SoCSDRAM):
         )
 
         if cpu == "libresoc":
-            self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12000))
+            self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12600))
             #self.comb += active_dbg_cr.eq(1)
 
             # get the CR