From: lkcl <lkcl@web>
Date: Tue, 4 Apr 2023 15:01:57 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~129
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e06a0faffba0c18150d3ba09c7b16f637885c40f;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index e1a405ed5..9f03918e5 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -124,7 +124,6 @@ The table for [[sv/svp64]] for `immed(RA)` which is `RM.MODE`
 |VLi| 1 | inv | CR-bit  | Rc=1: ffirst CR sel        |
 |VLi| 1 | inv | els RC1 |  Rc=0: ffirst z/nonz       |
 
-
 The `els` bit is only relevant when `RA.isvec` is clear: this indicates
 whether stride is unit or element:
 
@@ -493,6 +492,15 @@ one Element earlier.
            break                     # stop looping
 ```
 
+**Data-Dependent Fault-First on Store-Conditional**
+
+There are very few instructions that allow Rc=1 for Load/Store:
+one of those is the `stdcx.` and other Atomic Store-Conditional
+instructions.  It should be self-evident that being able to
+Vectorise and then truncate a sequence of Atomic Store-Conditional
+operations at the point where a store was not performed, should
+be pretty important.
+
 ## LOAD/STORE Elwidths <a name="elwidth"></a>
 
 Loads and Stores are almost unique in that the Power Scalar ISA