From: Luke Kenneth Casson Leighton Date: Tue, 25 Oct 2022 12:17:18 +0000 (+0100) Subject: redo the 3-in 1-out move of dsld/dsrd to EXT04 VA2-Form X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e06a474dec2e25cb31de825ce2f2267f51d417f9;p=openpower-isa.git redo the 3-in 1-out move of dsld/dsrd to EXT04 VA2-Form --- diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv index 1c67cbe7..e4dd1ce4 100644 --- a/openpower/isatables/minor_31.csv +++ b/openpower/isatables/minor_31.csv @@ -208,11 +208,3 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 0b1000110110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,tlbsync,X,,, 0b0000011110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,wait,X,,, 0b0100111100,LOGICAL,OP_XOR,RS,RB,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,xor,X,,, -0b0000111001,SHIFT_ROT,OP_DSHL,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg -0b0100111001,SHIFT_ROT,OP_DSHL,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg -0b1000111001,SHIFT_ROT,OP_DSHL,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg -0b1100111001,SHIFT_ROT,OP_DSHL,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg -0b0010111001,SHIFT_ROT,OP_DSHR,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg -0b0110111001,SHIFT_ROT,OP_DSHR,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg -0b1010111001,SHIFT_ROT,OP_DSHR,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg -0b1110111001,SHIFT_ROT,OP_DSHR,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/openpower/isatables/minor_4.csv b/openpower/isatables/minor_4.csv index 7d338877..b2426340 100644 --- a/openpower/isatables/minor_4.csv +++ b/openpower/isatables/minor_4.csv @@ -7,3 +7,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 51,ALU,OP_MADDLD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddld,VA,,, 58,ALU,OP_DIVMOD2DU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,divmod2du,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg 56,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,ONE,0,0,pcdec,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg +52,SHIFT_ROT,OP_DSHL,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg +53,SHIFT_ROT,OP_DSHL,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg +54,SHIFT_ROT,OP_DSHR,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg +55,SHIFT_ROT,OP_DSHR,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 7587d856..1a7bade8 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -587,10 +587,6 @@ def va_form(fields, XO): @_custom_insns( - _insn("dsld", PO=31, XO=0b00111001, Rc=0), - _insn("dsld.", PO=31, XO=0b00111001, Rc=1), - _insn("dsrd", PO=31, XO=0b10111001, Rc=0), - _insn("dsrd.", PO=31, XO=0b10111001, Rc=1), _insn("shadd", PO=22, XO=0b01101110, Rc=0), _insn("shadd.", PO=22, XO=0b01101110, Rc=1), _insn("shadduw", PO=22, XO=0b11101110, Rc=0), @@ -607,8 +603,32 @@ def Z23(fields, PO, XO, Rc): (RT, 6, 10), (RA, 11, 15), (RB, 16, 20), - (sm, 21, 22), - (XO, 23, 30), + (RC, 21, 25), + (XO, 26, 30), + (Rc, 31, 31), + ) + + +@_custom_insns( + _insn("dsld", XO=26, Rc=0), # minor_4=52 (26<<1 | Rc=0) + _insn("dsld.", XO=26, Rc=1), # minor_4=53 (26<<1 | Rc=1) + _insn("dsrd", XO=27, Rc=0), # minor_4=54 (27<<1 | Rc=0) + _insn("dsrd.", XO=27, Rc=1), # minor_4=55 (27<<1 | Rc=1) +) +def dsld_dsrd(fields, XO, Rc): + # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG + # 1.6.21.1 VA2-FORM + # |0 |6 |11 |16 |21 |26 |31| + # | PO | RT | RA | RB | RC | XO |Rc| + PO = 4 + (RT, RA, RB, RC) = fields + return instruction( + (PO, 0, 5), + (RT, 6, 10), + (RA, 11, 15), + (RB, 16, 20), + (RC, 21, 25), + (XO, 26, 30), (Rc, 31, 31), ) diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index 173acce0..d39717e2 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -399,14 +399,14 @@ class SVSTATETestCase(unittest.TestCase): def test_29_dsld_dsrd(self): expected = [ - "dsld 5,4,5,1", - "dsrd 5,4,5,2", + "dsld 5,4,5,3", + "dsrd 5,4,5,3", "dsld. 5,4,5,3", - "dsrd. 5,4,5,0", - "sv.dsld *5,4,5,1", - "sv.dsrd *5,4,5,2", - "sv.dsld. *5,4,5,3", - "sv.dsrd. *5,4,5,0", + "dsrd. 5,4,5,3", + "sv.dsld *6,4,5,3", + "sv.dsrd *6,4,5,3", + "sv.dsld. *6,4,5,3", + "sv.dsrd. *6,4,5,3", ] self._do_tst(expected) diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py index b6d86322..6a314212 100644 --- a/src/openpower/test/bigint/bigint_cases.py +++ b/src/openpower/test/bigint/bigint_cases.py @@ -34,7 +34,7 @@ class BigIntCases(TestAccumulatorBase): # FIXME: test more divmod2du special cases def case_dsld0(self): - prog = Program(list(SVP64Asm(["dsld 3,4,5,0"])), False) + prog = Program(list(SVP64Asm(["dsld 3,4,5,3"])), False) for sh in _SHIFT_TEST_RANGE: with self.subTest(sh=sh): gprs = [0] * 32 @@ -48,7 +48,7 @@ class BigIntCases(TestAccumulatorBase): self.add_case(prog, gprs, expected=e) def case_dsld1(self): - prog = Program(list(SVP64Asm(["dsld 3,4,5,1"])), False) + prog = Program(list(SVP64Asm(["dsld 3,3,5,4"])), False) for sh in _SHIFT_TEST_RANGE: with self.subTest(sh=sh): gprs = [0] * 32 @@ -62,7 +62,7 @@ class BigIntCases(TestAccumulatorBase): self.add_case(prog, gprs, expected=e) def case_dsld2(self): - prog = Program(list(SVP64Asm(["dsld 3,4,5,2"])), False) + prog = Program(list(SVP64Asm(["dsld 3,5,3,4"])), False) for sh in _SHIFT_TEST_RANGE: with self.subTest(sh=sh): gprs = [0] * 32 @@ -75,22 +75,8 @@ class BigIntCases(TestAccumulatorBase): e.intregs[3] = (v >> 64) % 2 ** 64 self.add_case(prog, gprs, expected=e) - def case_dsld3(self): - prog = Program(list(SVP64Asm(["dsld 3,4,5,3"])), False) - for sh in _SHIFT_TEST_RANGE: - with self.subTest(sh=sh): - gprs = [0] * 32 - gprs[3] = 0x123456789ABCDEF - gprs[4] = 0xFEDCBA9876543210 - gprs[5] = sh % 2 ** 64 - e = ExpectedState(pc=4, int_regs=gprs) - v = gprs[4] - v <<= sh % 64 - e.intregs[3] = (v >> 64) % 2 ** 64 - self.add_case(prog, gprs, expected=e) - def case_dsrd0(self): - prog = Program(list(SVP64Asm(["dsrd 3,4,5,0"])), False) + prog = Program(list(SVP64Asm(["dsrd 3,4,5,3"])), False) for sh in _SHIFT_TEST_RANGE: with self.subTest(sh=sh): gprs = [0] * 32 @@ -104,7 +90,7 @@ class BigIntCases(TestAccumulatorBase): self.add_case(prog, gprs, expected=e) def case_dsrd1(self): - prog = Program(list(SVP64Asm(["dsrd 3,4,5,1"])), False) + prog = Program(list(SVP64Asm(["dsrd 3,3,5,4"])), False) for sh in _SHIFT_TEST_RANGE: with self.subTest(sh=sh): gprs = [0] * 32 @@ -118,7 +104,7 @@ class BigIntCases(TestAccumulatorBase): self.add_case(prog, gprs, expected=e) def case_dsrd2(self): - prog = Program(list(SVP64Asm(["dsrd 3,4,5,2"])), False) + prog = Program(list(SVP64Asm(["dsrd 3,5,3,4"])), False) for sh in _SHIFT_TEST_RANGE: with self.subTest(sh=sh): gprs = [0] * 32 @@ -131,20 +117,6 @@ class BigIntCases(TestAccumulatorBase): e.intregs[3] = v % 2 ** 64 self.add_case(prog, gprs, expected=e) - def case_dsrd3(self): - prog = Program(list(SVP64Asm(["dsrd 3,4,5,3"])), False) - for sh in _SHIFT_TEST_RANGE: - with self.subTest(sh=sh): - gprs = [0] * 32 - gprs[3] = 0x123456789ABCDEF - gprs[4] = 0xFEDCBA9876543210 - gprs[5] = sh % 2 ** 64 - e = ExpectedState(pc=4, int_regs=gprs) - v = gprs[4] << 64 - v >>= sh % 64 - e.intregs[3] = v % 2 ** 64 - self.add_case(prog, gprs, expected=e) - class SVP64BigIntCases(TestAccumulatorBase): def case_sv_bigint_add(self):