From: Eddie Hung Date: Sat, 20 Jul 2019 05:47:08 +0000 (-0700) Subject: Restore old ffY behaviour X-Git-Tag: working-ls180~1039^2~312 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e0720a8018702a2b4de108363a51c8bffc287b55;p=yosys.git Restore old ffY behaviour --- diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index fb5fe0951..e4c6238c5 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -3,7 +3,6 @@ pattern ice40_dsp state clock state clock_pol state sigA sigB sigY sigS -state sigYused state addAB muxAB match mul @@ -54,28 +53,18 @@ code sigB clock clock_pol } endcode -// Extract the bits of Y that actually have a consumer -// (as opposed to being a sign extension) -code sigY sigYused - sigY = port(mul, \Y); - int i; - for (i = GetSize(sigY); i > 0; i--) - if (nusers(sigY[i-1]) > 1) - break; - sigYused = sigY.extract(0, i); -endcode - match ffY select ffY->type.in($dff) select nusers(port(ffY, \D)) == 2 - filter param(ffY, \WIDTH).as_int() >= GetSize(sigYused) - filter includes(port(ffY, \D).to_sigbit_set(), sigYused.to_sigbit_set()) + index port(ffY, \D) === port(mul, \Y) optional endmatch -code clock clock_pol sigY +code sigY clock clock_pol + sigY = port(mul, \Y); + if (ffY) { - sigY.replace(port(ffY, \D), port(ffY, \Q)); + sigY = port(ffY, \Q); SigBit c = port(ffY, \CLK).as_bit(); bool cp = param(ffY, \CLK_POLARITY).as_bool();