From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Tue, 25 May 2021 00:12:55 +0000 (+0200)
Subject: Add memory_narrow pass.
X-Git-Tag: yosys-0.10~173
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e0736c1622c60980ddf9b989e9c3e2acc4403135;p=yosys.git

Add memory_narrow pass.
---

diff --git a/passes/memory/Makefile.inc b/passes/memory/Makefile.inc
index e468c3a07..5a2c4ecfc 100644
--- a/passes/memory/Makefile.inc
+++ b/passes/memory/Makefile.inc
@@ -8,4 +8,5 @@ OBJS += passes/memory/memory_bram.o
 OBJS += passes/memory/memory_map.o
 OBJS += passes/memory/memory_memx.o
 OBJS += passes/memory/memory_nordff.o
+OBJS += passes/memory/memory_narrow.o
 
diff --git a/passes/memory/memory_narrow.cc b/passes/memory/memory_narrow.cc
new file mode 100644
index 000000000..cf5e43465
--- /dev/null
+++ b/passes/memory/memory_narrow.cc
@@ -0,0 +1,67 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2020  Marcelina Kościelnicka <mwk@0x04.net>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include "kernel/mem.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct MemoryNarrowPass : public Pass {
+	MemoryNarrowPass() : Pass("memory_narrow", "split up wide memory ports") { }
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    memory_narrow [options] [selection]\n");
+		log("\n");
+		log("This pass splits up wide memory ports into several narrow ports.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing MEMORY_NARROW pass (splitting up wide memory ports).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules()) {
+			for (auto &mem : Mem::get_selected_memories(module))
+			{
+				bool wide = false;
+				for (auto &port : mem.rd_ports)
+					if (port.wide_log2)
+						wide = true;
+				for (auto &port : mem.wr_ports)
+					if (port.wide_log2)
+						wide = true;
+				if (wide) {
+					mem.narrow();
+					mem.emit();
+				}
+			}
+		}
+	}
+} MemoryNarrowPass;
+
+PRIVATE_NAMESPACE_END