From: Segher Boessenkool Date: Wed, 7 Jun 2017 15:22:33 +0000 (+0200) Subject: rs6000: Remove TARGET_SPE and TARGET_SPE_ABI and friends X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e075a6ccbf3d92136e918661bb8dde5add99c9a2;p=gcc.git rs6000: Remove TARGET_SPE and TARGET_SPE_ABI and friends * config/rs6000/rs6000-common.c (rs6000_handle_option): Remove SPE ABI handling. * config/rs6000/paired.md (paired_negv2sf2): Rename to negv2sf2. (paired_absv2sf2, paired_addv2sf3, paired_subv2sf3, paired_mulv2sf3, paired_divv2sf3): Similar. * config/rs6000/predicates.md: Replace TARGET_SPE, TARGET_SPE_ABI, SPE_VECTOR_MODE and SPE_HIGH_REGNO_P by 0; simplify. * config/rs6000/rs6000-builtin.def: Delete RS6000_BUILTIN_E and RS6000_BUILTIN_S. Delete BU_SPE_1, BU_SPE_2, BU_SPE_3, BU_SPE_E, BU_SPE_P, and BU_SPE_X. Rename the paired_* instruction patterns. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Do not define __SPE__. * config/rs6000/rs6000-protos.h (invalid_e500_subreg): Delete. * config/rs6000/rs6000.c: Delete RS6000_BUILTIN_E and RS6000_BUILTIN_S. (struct rs6000_stack): Delete fields spe_gp_save_offset, spe_gp_size, spe_padding_size, and spe_64bit_regs_used. Replace TARGET_SPE and TARGET_SPE_ABI with 0, simplify. Replace SPE_VECTOR_MODE with PAIRED_VECTOR_MODE. (struct machine_function): Delete field spe_insn_chain_scanned_p. (spe_func_has_64bit_regs_p): Delete. (spe_expand_predicate_builtin): Delete. (spe_expand_evsel_builtin): Delete. (TARGET_DWARF_REGISTER_SPAN): Do not define. (TARGET_MEMBER_TYPE_FORCES_BLK): Do not define. (invalid_e500_subreg): Delete. (rs6000_legitimize_address): Always force_reg op2 as well, for paired single memory accesses. (rs6000_member_type_forces_blk): Delete. (rs6000_spe_function_arg): Delete. (rs6000_expand_unop_builtin): Delete SPE handling. (rs6000_expand_binop_builtin): Ditto. (spe_expand_stv_builtin): Delete. (bdesc_2arg_spe): Delete. (spe_expand_builtin): Delete. (spe_expand_predicate_builtin): Delete. (spe_expand_evsel_builtin): Delete. (rs6000_invalid_builtin): Remove RS6000_BTM_SPE handling. (spe_init_builtins): Delete. (spe_func_has_64bit_regs_p): Delete. (savres_routine_name): Delete "info" parameter. Adjust callers. (rs6000_emit_stack_reset): Ditto. (rs6000_dwarf_register_span): Delete. * config/rs6000/rs6000.h (TARGET_SPE_ABI, TARGET_SPE, UNITS_PER_SPE_WORD, SPE_HIGH_REGNO_P, SPE_SIMD_REGNO_P, SPE_VECTOR_MODE, RS6000_BTM_SPE, RS6000_BUILTIN_E, RS6000_BUILTIN_S): Delete. * config/rs6000/rs6000.md (FIRST_SPE_HIGH_REGNO, LAST_SPE_HIGH_REGNO): Delete. * config/rs6000/rs6000.opt (-mabi=spe, -mabi=no-spe): Delete. * config/rs6000/spe.md: Delete every pattern that uses TARGET_SPE. * config/rs6000/vector.md (absv2sf2, negv2sf2, addv2sf3, subv2sf3, mulv2sf3, divv2sf3): Delete expanders. From-SVN: r248980 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c7f9ebc93bd..444ffb9c824 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,59 @@ +2017-06-07 Segher Boessenkool + + * config/rs6000/rs6000-common.c (rs6000_handle_option): Remove + SPE ABI handling. + * config/rs6000/paired.md (paired_negv2sf2): Rename to negv2sf2. + (paired_absv2sf2, paired_addv2sf3, paired_subv2sf3, paired_mulv2sf3, + paired_divv2sf3): Similar. + * config/rs6000/predicates.md: Replace TARGET_SPE, TARGET_SPE_ABI, + SPE_VECTOR_MODE and SPE_HIGH_REGNO_P by 0; simplify. + * config/rs6000/rs6000-builtin.def: Delete RS6000_BUILTIN_E and + RS6000_BUILTIN_S. + Delete BU_SPE_1, BU_SPE_2, BU_SPE_3, BU_SPE_E, BU_SPE_P, and BU_SPE_X. + Rename the paired_* instruction patterns. + * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Do not + define __SPE__. + * config/rs6000/rs6000-protos.h (invalid_e500_subreg): Delete. + * config/rs6000/rs6000.c: Delete RS6000_BUILTIN_E and RS6000_BUILTIN_S. + (struct rs6000_stack): Delete fields spe_gp_save_offset, spe_gp_size, + spe_padding_size, and spe_64bit_regs_used. Replace TARGET_SPE and + TARGET_SPE_ABI with 0, simplify. Replace SPE_VECTOR_MODE with + PAIRED_VECTOR_MODE. + (struct machine_function): Delete field spe_insn_chain_scanned_p. + (spe_func_has_64bit_regs_p): Delete. + (spe_expand_predicate_builtin): Delete. + (spe_expand_evsel_builtin): Delete. + (TARGET_DWARF_REGISTER_SPAN): Do not define. + (TARGET_MEMBER_TYPE_FORCES_BLK): Do not define. + (invalid_e500_subreg): Delete. + (rs6000_legitimize_address): Always force_reg op2 as well, for + paired single memory accesses. + (rs6000_member_type_forces_blk): Delete. + (rs6000_spe_function_arg): Delete. + (rs6000_expand_unop_builtin): Delete SPE handling. + (rs6000_expand_binop_builtin): Ditto. + (spe_expand_stv_builtin): Delete. + (bdesc_2arg_spe): Delete. + (spe_expand_builtin): Delete. + (spe_expand_predicate_builtin): Delete. + (spe_expand_evsel_builtin): Delete. + (rs6000_invalid_builtin): Remove RS6000_BTM_SPE handling. + (spe_init_builtins): Delete. + (spe_func_has_64bit_regs_p): Delete. + (savres_routine_name): Delete "info" parameter. Adjust callers. + (rs6000_emit_stack_reset): Ditto. + (rs6000_dwarf_register_span): Delete. + * config/rs6000/rs6000.h (TARGET_SPE_ABI, TARGET_SPE, + UNITS_PER_SPE_WORD, SPE_HIGH_REGNO_P, SPE_SIMD_REGNO_P, + SPE_VECTOR_MODE, RS6000_BTM_SPE, RS6000_BUILTIN_E, RS6000_BUILTIN_S): + Delete. + * config/rs6000/rs6000.md (FIRST_SPE_HIGH_REGNO, LAST_SPE_HIGH_REGNO): + Delete. + * config/rs6000/rs6000.opt (-mabi=spe, -mabi=no-spe): Delete. + * config/rs6000/spe.md: Delete every pattern that uses TARGET_SPE. + * config/rs6000/vector.md (absv2sf2, negv2sf2, addv2sf3, subv2sf3, + mulv2sf3, divv2sf3): Delete expanders. + 2017-06-07 Segher Boessenkool config/rs6000/rs6000.md (UNSPEC_MV_CR_GT): Delete. diff --git a/gcc/common/config/rs6000/rs6000-common.c b/gcc/common/config/rs6000/rs6000-common.c index 3c0106ae555..07537543ddc 100644 --- a/gcc/common/config/rs6000/rs6000-common.c +++ b/gcc/common/config/rs6000/rs6000-common.c @@ -207,15 +207,6 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set, break; #endif - case OPT_mabi_altivec: - /* Enabling the AltiVec ABI turns off the SPE ABI. */ - opts->x_rs6000_spe_abi = 0; - break; - - case OPT_mabi_spe: - opts->x_rs6000_altivec_abi = 0; - break; - case OPT_mlong_double_: if (value != 64 && value != 128) { diff --git a/gcc/config/rs6000/paired.md b/gcc/config/rs6000/paired.md index 09123eec887..c9f95867c0f 100644 --- a/gcc/config/rs6000/paired.md +++ b/gcc/config/rs6000/paired.md @@ -26,7 +26,7 @@ UNSPEC_EXTODD_V2SF ]) -(define_insn "paired_negv2sf2" +(define_insn "negv2sf2" [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))] "TARGET_PAIRED_FLOAT" @@ -40,7 +40,7 @@ "ps_rsqrte %0,%1" [(set_attr "type" "fp")]) -(define_insn "paired_absv2sf2" +(define_insn "absv2sf2" [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))] "TARGET_PAIRED_FLOAT" @@ -54,7 +54,7 @@ "ps_nabs %0,%1" [(set_attr "type" "fp")]) -(define_insn "paired_addv2sf3" +(define_insn "addv2sf3" [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f") (match_operand:V2SF 2 "gpc_reg_operand" "f")))] @@ -62,7 +62,7 @@ "ps_add %0,%1,%2" [(set_attr "type" "fp")]) -(define_insn "paired_subv2sf3" +(define_insn "subv2sf3" [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f") (match_operand:V2SF 2 "gpc_reg_operand" "f")))] @@ -70,7 +70,7 @@ "ps_sub %0,%1,%2" [(set_attr "type" "fp")]) -(define_insn "paired_mulv2sf3" +(define_insn "mulv2sf3" [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f") (match_operand:V2SF 2 "gpc_reg_operand" "f")))] @@ -85,7 +85,7 @@ "ps_res %0,%1" [(set_attr "type" "fp")]) -(define_insn "paired_divv2sf3" +(define_insn "divv2sf3" [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f") (match_operand:V2SF 2 "gpc_reg_operand" "f")))] diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 11aecbd1b89..4edfdbbe0d9 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -299,9 +299,6 @@ (define_predicate "gpc_reg_operand" (match_operand 0 "register_operand") { - if (TARGET_SPE && invalid_e500_subreg (op, mode)) - return 0; - if (GET_CODE (op) == SUBREG) { if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) @@ -331,9 +328,6 @@ (define_predicate "int_reg_operand" (match_operand 0 "register_operand") { - if (TARGET_SPE && invalid_e500_subreg (op, mode)) - return 0; - if (GET_CODE (op) == SUBREG) { if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) @@ -357,9 +351,6 @@ (define_predicate "int_reg_operand_not_pseudo" (match_operand 0 "register_operand") { - if (TARGET_SPE && invalid_e500_subreg (op, mode)) - return 0; - if (GET_CODE (op) == SUBREG) op = SUBREG_REG (op); @@ -711,32 +702,6 @@ return easy_altivec_constant (op, mode); } - if (SPE_VECTOR_MODE (mode)) - { - int cst, cst2; - if (zero_constant (op, mode)) - return true; - if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) - return false; - - /* Limit SPE vectors to 15 bits signed. These we can generate with: - li r0, CONSTANT1 - evmergelo r0, r0, r0 - li r0, CONSTANT2 - - I don't know how efficient it would be to allow bigger constants, - considering we'll have an extra 'ori' for every 'li'. I doubt 5 - instructions is better than a 64-bit memory load, but I don't - have the e500 timing specs. */ - if (mode == V2SImode) - { - cst = INTVAL (CONST_VECTOR_ELT (op, 0)); - cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); - return cst >= -0x7fff && cst <= 0x7fff - && cst2 >= -0x7fff && cst2 <= 0x7fff; - } - } - return false; }) @@ -1135,12 +1100,6 @@ && easy_vector_constant (op, mode)) return 1; - /* Do not allow invalid E500 subregs. */ - if (TARGET_SPE - && GET_CODE (op) == SUBREG - && invalid_e500_subreg (op, mode)) - return 0; - /* For floating-point or multi-word mode, the only remaining valid type is a register. */ if (SCALAR_FLOAT_MODE_P (mode) @@ -1199,16 +1158,10 @@ return gpc_reg_operand (op, mode); }) -;; Return true if OP is a non-immediate operand and not an invalid -;; SUBREG operation on the e500. +;; Return true if OP is a non-immediate operand. (define_predicate "rs6000_nonimmediate_operand" (match_code "reg,subreg,mem") { - if (TARGET_SPE - && GET_CODE (op) == SUBREG - && invalid_e500_subreg (op, mode)) - return 0; - return nonimmediate_operand (op, mode); }) diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index de6b2ccee1f..241c4395ce9 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -30,11 +30,9 @@ RS6000_BUILTIN_3 -- 3 arg builtins RS6000_BUILTIN_A -- ABS builtins RS6000_BUILTIN_D -- DST builtins - RS6000_BUILTIN_E -- SPE EVSEL builtins. RS6000_BUILTIN_H -- HTM builtins RS6000_BUILTIN_P -- Altivec, VSX, ISA 2.07 vector predicate builtins RS6000_BUILTIN_Q -- Paired floating point VSX predicate builtins - RS6000_BUILTIN_S -- SPE predicate builtins RS6000_BUILTIN_X -- special builtins Each of the above macros takes 4 arguments: @@ -68,10 +66,6 @@ #error "RS6000_BUILTIN_D is not defined." #endif -#ifndef RS6000_BUILTIN_E - #error "RS6000_BUILTIN_E is not defined." -#endif - #ifndef RS6000_BUILTIN_H #error "RS6000_BUILTIN_H is not defined." #endif @@ -84,10 +78,6 @@ #error "RS6000_BUILTIN_Q is not defined." #endif -#ifndef RS6000_BUILTIN_S - #error "RS6000_BUILTIN_S is not defined." -#endif - #ifndef RS6000_BUILTIN_X #error "RS6000_BUILTIN_X is not defined." #endif @@ -551,55 +541,6 @@ | RS6000_BTC_VOID), \ CODE_FOR_ ## ICODE) /* ICODE */ -/* SPE convenience macros. */ -#define BU_SPE_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_SPE_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_SPE_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_3 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_SPE_E(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_E (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_EVSEL), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_SPE_P(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_S (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_PREDICATE), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_SPE_X(ENUM, NAME, ATTR) \ - RS6000_BUILTIN_X (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_nothing) /* ICODE */ - /* Paired floating point convenience macros. */ #define BU_PAIRED_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ @@ -2370,10 +2311,10 @@ BU_PAIRED_3 (SUM1, "sum1", FP, paired_sum1) BU_PAIRED_3 (SELV2SF4, "selv2sf4", CONST, selv2sf4) /* 2 argument paired floating point builtins. */ -BU_PAIRED_2 (DIVV2SF3, "divv2sf3", FP, paired_divv2sf3) -BU_PAIRED_2 (ADDV2SF3, "addv2sf3", FP, paired_addv2sf3) -BU_PAIRED_2 (SUBV2SF3, "subv2sf3", FP, paired_subv2sf3) -BU_PAIRED_2 (MULV2SF3, "mulv2sf3", FP, paired_mulv2sf3) +BU_PAIRED_2 (DIVV2SF3, "divv2sf3", FP, divv2sf3) +BU_PAIRED_2 (ADDV2SF3, "addv2sf3", FP, addv2sf3) +BU_PAIRED_2 (SUBV2SF3, "subv2sf3", FP, subv2sf3) +BU_PAIRED_2 (MULV2SF3, "mulv2sf3", FP, mulv2sf3) BU_PAIRED_2 (MULS0, "muls0", FP, paired_muls0) BU_PAIRED_2 (MULS1, "muls1", FP, paired_muls1) BU_PAIRED_2 (MERGE00, "merge00", CONST, paired_merge00) @@ -2382,9 +2323,9 @@ BU_PAIRED_2 (MERGE10, "merge10", CONST, paired_merge10) BU_PAIRED_2 (MERGE11, "merge11", CONST, paired_merge11) /* 1 argument paired floating point builtin functions. */ -BU_PAIRED_1 (ABSV2SF2, "absv2sf2", CONST, paired_absv2sf2) +BU_PAIRED_1 (ABSV2SF2, "absv2sf2", CONST, absv2sf2) BU_PAIRED_1 (NABSV2SF2, "nabsv2sf2", CONST, nabsv2sf2) -BU_PAIRED_1 (NEGV2SF2, "negv2sf2", CONST, paired_negv2sf2) +BU_PAIRED_1 (NEGV2SF2, "negv2sf2", CONST, negv2sf2) BU_PAIRED_1 (SQRTV2SF2, "sqrtv2sf2", FP, sqrtv2sf2) BU_PAIRED_1 (RESV2SF, "resv2sf2", FP, resv2sf2) @@ -2395,248 +2336,6 @@ BU_PAIRED_X (LX, "lx", MISC) /* Paired predicates. */ BU_PAIRED_P (CMPU0, "cmpu0", CONST, paired_cmpu0) BU_PAIRED_P (CMPU1, "cmpu1", CONST, paired_cmpu1) - -/* PowerPC E500 builtins (SPE). */ - -BU_SPE_2 (EVADDW, "evaddw", MISC, addv2si3) -BU_SPE_2 (EVAND, "evand", MISC, andv2si3) -BU_SPE_2 (EVANDC, "evandc", MISC, spe_evandc) -BU_SPE_2 (EVDIVWS, "evdivws", MISC, divv2si3) -BU_SPE_2 (EVDIVWU, "evdivwu", MISC, spe_evdivwu) -BU_SPE_2 (EVEQV, "eveqv", MISC, spe_eveqv) -BU_SPE_2 (EVFSADD, "evfsadd", MISC, spe_evfsadd) -BU_SPE_2 (EVFSDIV, "evfsdiv", MISC, spe_evfsdiv) -BU_SPE_2 (EVFSMUL, "evfsmul", MISC, spe_evfsmul) -BU_SPE_2 (EVFSSUB, "evfssub", MISC, spe_evfssub) -BU_SPE_2 (EVMERGEHI, "evmergehi", MISC, spe_evmergehi) -BU_SPE_2 (EVMERGEHILO, "evmergehilo", MISC, spe_evmergehilo) -BU_SPE_2 (EVMERGELO, "evmergelo", MISC, spe_evmergelo) -BU_SPE_2 (EVMERGELOHI, "evmergelohi", MISC, spe_evmergelohi) -BU_SPE_2 (EVMHEGSMFAA, "evmhegsmfaa", MISC, spe_evmhegsmfaa) -BU_SPE_2 (EVMHEGSMFAN, "evmhegsmfan", MISC, spe_evmhegsmfan) -BU_SPE_2 (EVMHEGSMIAA, "evmhegsmiaa", MISC, spe_evmhegsmiaa) -BU_SPE_2 (EVMHEGSMIAN, "evmhegsmian", MISC, spe_evmhegsmian) -BU_SPE_2 (EVMHEGUMIAA, "evmhegumiaa", MISC, spe_evmhegumiaa) -BU_SPE_2 (EVMHEGUMIAN, "evmhegumian", MISC, spe_evmhegumian) -BU_SPE_2 (EVMHESMF, "evmhesmf", MISC, spe_evmhesmf) -BU_SPE_2 (EVMHESMFA, "evmhesmfa", MISC, spe_evmhesmfa) -BU_SPE_2 (EVMHESMFAAW, "evmhesmfaaw", MISC, spe_evmhesmfaaw) -BU_SPE_2 (EVMHESMFANW, "evmhesmfanw", MISC, spe_evmhesmfanw) -BU_SPE_2 (EVMHESMI, "evmhesmi", MISC, spe_evmhesmi) -BU_SPE_2 (EVMHESMIA, "evmhesmia", MISC, spe_evmhesmia) -BU_SPE_2 (EVMHESMIAAW, "evmhesmiaaw", MISC, spe_evmhesmiaaw) -BU_SPE_2 (EVMHESMIANW, "evmhesmianw", MISC, spe_evmhesmianw) -BU_SPE_2 (EVMHESSF, "evmhessf", MISC, spe_evmhessf) -BU_SPE_2 (EVMHESSFA, "evmhessfa", MISC, spe_evmhessfa) -BU_SPE_2 (EVMHESSFAAW, "evmhessfaaw", MISC, spe_evmhessfaaw) -BU_SPE_2 (EVMHESSFANW, "evmhessfanw", MISC, spe_evmhessfanw) -BU_SPE_2 (EVMHESSIAAW, "evmhessiaaw", MISC, spe_evmhessiaaw) -BU_SPE_2 (EVMHESSIANW, "evmhessianw", MISC, spe_evmhessianw) -BU_SPE_2 (EVMHEUMI, "evmheumi", MISC, spe_evmheumi) -BU_SPE_2 (EVMHEUMIA, "evmheumia", MISC, spe_evmheumia) -BU_SPE_2 (EVMHEUMIAAW, "evmheumiaaw", MISC, spe_evmheumiaaw) -BU_SPE_2 (EVMHEUMIANW, "evmheumianw", MISC, spe_evmheumianw) -BU_SPE_2 (EVMHEUSIAAW, "evmheusiaaw", MISC, spe_evmheusiaaw) -BU_SPE_2 (EVMHEUSIANW, "evmheusianw", MISC, spe_evmheusianw) -BU_SPE_2 (EVMHOGSMFAA, "evmhogsmfaa", MISC, spe_evmhogsmfaa) -BU_SPE_2 (EVMHOGSMFAN, "evmhogsmfan", MISC, spe_evmhogsmfan) -BU_SPE_2 (EVMHOGSMIAA, "evmhogsmiaa", MISC, spe_evmhogsmiaa) -BU_SPE_2 (EVMHOGSMIAN, "evmhogsmian", MISC, spe_evmhogsmian) -BU_SPE_2 (EVMHOGUMIAA, "evmhogumiaa", MISC, spe_evmhogumiaa) -BU_SPE_2 (EVMHOGUMIAN, "evmhogumian", MISC, spe_evmhogumian) -BU_SPE_2 (EVMHOSMF, "evmhosmf", MISC, spe_evmhosmf) -BU_SPE_2 (EVMHOSMFA, "evmhosmfa", MISC, spe_evmhosmfa) -BU_SPE_2 (EVMHOSMFAAW, "evmhosmfaaw", MISC, spe_evmhosmfaaw) -BU_SPE_2 (EVMHOSMFANW, "evmhosmfanw", MISC, spe_evmhosmfanw) -BU_SPE_2 (EVMHOSMI, "evmhosmi", MISC, spe_evmhosmi) -BU_SPE_2 (EVMHOSMIA, "evmhosmia", MISC, spe_evmhosmia) -BU_SPE_2 (EVMHOSMIAAW, "evmhosmiaaw", MISC, spe_evmhosmiaaw) -BU_SPE_2 (EVMHOSMIANW, "evmhosmianw", MISC, spe_evmhosmianw) -BU_SPE_2 (EVMHOSSF, "evmhossf", MISC, spe_evmhossf) -BU_SPE_2 (EVMHOSSFA, "evmhossfa", MISC, spe_evmhossfa) -BU_SPE_2 (EVMHOSSFAAW, "evmhossfaaw", MISC, spe_evmhossfaaw) -BU_SPE_2 (EVMHOSSFANW, "evmhossfanw", MISC, spe_evmhossfanw) -BU_SPE_2 (EVMHOSSIAAW, "evmhossiaaw", MISC, spe_evmhossiaaw) -BU_SPE_2 (EVMHOSSIANW, "evmhossianw", MISC, spe_evmhossianw) -BU_SPE_2 (EVMHOUMI, "evmhoumi", MISC, spe_evmhoumi) -BU_SPE_2 (EVMHOUMIA, "evmhoumia", MISC, spe_evmhoumia) -BU_SPE_2 (EVMHOUMIAAW, "evmhoumiaaw", MISC, spe_evmhoumiaaw) -BU_SPE_2 (EVMHOUMIANW, "evmhoumianw", MISC, spe_evmhoumianw) -BU_SPE_2 (EVMHOUSIAAW, "evmhousiaaw", MISC, spe_evmhousiaaw) -BU_SPE_2 (EVMHOUSIANW, "evmhousianw", MISC, spe_evmhousianw) -BU_SPE_2 (EVMWHSMF, "evmwhsmf", MISC, spe_evmwhsmf) -BU_SPE_2 (EVMWHSMFA, "evmwhsmfa", MISC, spe_evmwhsmfa) -BU_SPE_2 (EVMWHSMI, "evmwhsmi", MISC, spe_evmwhsmi) -BU_SPE_2 (EVMWHSMIA, "evmwhsmia", MISC, spe_evmwhsmia) -BU_SPE_2 (EVMWHSSF, "evmwhssf", MISC, spe_evmwhssf) -BU_SPE_2 (EVMWHSSFA, "evmwhssfa", MISC, spe_evmwhssfa) -BU_SPE_2 (EVMWHUMI, "evmwhumi", MISC, spe_evmwhumi) -BU_SPE_2 (EVMWHUMIA, "evmwhumia", MISC, spe_evmwhumia) -BU_SPE_2 (EVMWLSMIAAW, "evmwlsmiaaw", MISC, spe_evmwlsmiaaw) -BU_SPE_2 (EVMWLSMIANW, "evmwlsmianw", MISC, spe_evmwlsmianw) -BU_SPE_2 (EVMWLSSIAAW, "evmwlssiaaw", MISC, spe_evmwlssiaaw) -BU_SPE_2 (EVMWLSSIANW, "evmwlssianw", MISC, spe_evmwlssianw) -BU_SPE_2 (EVMWLUMI, "evmwlumi", MISC, spe_evmwlumi) -BU_SPE_2 (EVMWLUMIA, "evmwlumia", MISC, spe_evmwlumia) -BU_SPE_2 (EVMWLUMIAAW, "evmwlumiaaw", MISC, spe_evmwlumiaaw) -BU_SPE_2 (EVMWLUMIANW, "evmwlumianw", MISC, spe_evmwlumianw) -BU_SPE_2 (EVMWLUSIAAW, "evmwlusiaaw", MISC, spe_evmwlusiaaw) -BU_SPE_2 (EVMWLUSIANW, "evmwlusianw", MISC, spe_evmwlusianw) -BU_SPE_2 (EVMWSMF, "evmwsmf", MISC, spe_evmwsmf) -BU_SPE_2 (EVMWSMFA, "evmwsmfa", MISC, spe_evmwsmfa) -BU_SPE_2 (EVMWSMFAA, "evmwsmfaa", MISC, spe_evmwsmfaa) -BU_SPE_2 (EVMWSMFAN, "evmwsmfan", MISC, spe_evmwsmfan) -BU_SPE_2 (EVMWSMI, "evmwsmi", MISC, spe_evmwsmi) -BU_SPE_2 (EVMWSMIA, "evmwsmia", MISC, spe_evmwsmia) -BU_SPE_2 (EVMWSMIAA, "evmwsmiaa", MISC, spe_evmwsmiaa) -BU_SPE_2 (EVMWSMIAN, "evmwsmian", MISC, spe_evmwsmian) -BU_SPE_2 (EVMWSSF, "evmwssf", MISC, spe_evmwssf) -BU_SPE_2 (EVMWSSFA, "evmwssfa", MISC, spe_evmwssfa) -BU_SPE_2 (EVMWSSFAA, "evmwssfaa", MISC, spe_evmwssfaa) -BU_SPE_2 (EVMWSSFAN, "evmwssfan", MISC, spe_evmwssfan) -BU_SPE_2 (EVMWUMI, "evmwumi", MISC, spe_evmwumi) -BU_SPE_2 (EVMWUMIA, "evmwumia", MISC, spe_evmwumia) -BU_SPE_2 (EVMWUMIAA, "evmwumiaa", MISC, spe_evmwumiaa) -BU_SPE_2 (EVMWUMIAN, "evmwumian", MISC, spe_evmwumian) -BU_SPE_2 (EVNAND, "evnand", MISC, spe_evnand) -BU_SPE_2 (EVNOR, "evnor", MISC, spe_evnor) -BU_SPE_2 (EVOR, "evor", MISC, spe_evor) -BU_SPE_2 (EVORC, "evorc", MISC, spe_evorc) -BU_SPE_2 (EVRLW, "evrlw", MISC, spe_evrlw) -BU_SPE_2 (EVSLW, "evslw", MISC, spe_evslw) -BU_SPE_2 (EVSRWS, "evsrws", MISC, spe_evsrws) -BU_SPE_2 (EVSRWU, "evsrwu", MISC, spe_evsrwu) -BU_SPE_2 (EVSUBFW, "evsubfw", MISC, subv2si3) - -/* SPE binary operations expecting a 5-bit unsigned literal. */ -BU_SPE_2 (EVADDIW, "evaddiw", MISC, spe_evaddiw) - -BU_SPE_2 (EVRLWI, "evrlwi", MISC, spe_evrlwi) -BU_SPE_2 (EVSLWI, "evslwi", MISC, spe_evslwi) -BU_SPE_2 (EVSRWIS, "evsrwis", MISC, spe_evsrwis) -BU_SPE_2 (EVSRWIU, "evsrwiu", MISC, spe_evsrwiu) -BU_SPE_2 (EVSUBIFW, "evsubifw", MISC, spe_evsubifw) -BU_SPE_2 (EVMWHSSFAA, "evmwhssfaa", MISC, spe_evmwhssfaa) -BU_SPE_2 (EVMWHSSMAA, "evmwhssmaa", MISC, spe_evmwhssmaa) -BU_SPE_2 (EVMWHSMFAA, "evmwhsmfaa", MISC, spe_evmwhsmfaa) -BU_SPE_2 (EVMWHSMIAA, "evmwhsmiaa", MISC, spe_evmwhsmiaa) -BU_SPE_2 (EVMWHUSIAA, "evmwhusiaa", MISC, spe_evmwhusiaa) -BU_SPE_2 (EVMWHUMIAA, "evmwhumiaa", MISC, spe_evmwhumiaa) -BU_SPE_2 (EVMWHSSFAN, "evmwhssfan", MISC, spe_evmwhssfan) -BU_SPE_2 (EVMWHSSIAN, "evmwhssian", MISC, spe_evmwhssian) -BU_SPE_2 (EVMWHSMFAN, "evmwhsmfan", MISC, spe_evmwhsmfan) -BU_SPE_2 (EVMWHSMIAN, "evmwhsmian", MISC, spe_evmwhsmian) -BU_SPE_2 (EVMWHUSIAN, "evmwhusian", MISC, spe_evmwhusian) -BU_SPE_2 (EVMWHUMIAN, "evmwhumian", MISC, spe_evmwhumian) -BU_SPE_2 (EVMWHGSSFAA, "evmwhgssfaa", MISC, spe_evmwhgssfaa) -BU_SPE_2 (EVMWHGSMFAA, "evmwhgsmfaa", MISC, spe_evmwhgsmfaa) -BU_SPE_2 (EVMWHGSMIAA, "evmwhgsmiaa", MISC, spe_evmwhgsmiaa) -BU_SPE_2 (EVMWHGUMIAA, "evmwhgumiaa", MISC, spe_evmwhgumiaa) -BU_SPE_2 (EVMWHGSSFAN, "evmwhgssfan", MISC, spe_evmwhgssfan) -BU_SPE_2 (EVMWHGSMFAN, "evmwhgsmfan", MISC, spe_evmwhgsmfan) -BU_SPE_2 (EVMWHGSMIAN, "evmwhgsmian", MISC, spe_evmwhgsmian) -BU_SPE_2 (EVMWHGUMIAN, "evmwhgumian", MISC, spe_evmwhgumian) -BU_SPE_2 (BRINC, "brinc", MISC, spe_brinc) -BU_SPE_2 (EVXOR, "evxor", MISC, xorv2si3) - -/* SPE predicate builtins. */ -BU_SPE_P (EVCMPEQ, "evcmpeq", MISC, spe_evcmpeq) -BU_SPE_P (EVCMPGTS, "evcmpgts", MISC, spe_evcmpgts) -BU_SPE_P (EVCMPGTU, "evcmpgtu", MISC, spe_evcmpgtu) -BU_SPE_P (EVCMPLTS, "evcmplts", MISC, spe_evcmplts) -BU_SPE_P (EVCMPLTU, "evcmpltu", MISC, spe_evcmpltu) -BU_SPE_P (EVFSCMPEQ, "evfscmpeq", MISC, spe_evfscmpeq) -BU_SPE_P (EVFSCMPGT, "evfscmpgt", MISC, spe_evfscmpgt) -BU_SPE_P (EVFSCMPLT, "evfscmplt", MISC, spe_evfscmplt) -BU_SPE_P (EVFSTSTEQ, "evfststeq", MISC, spe_evfststeq) -BU_SPE_P (EVFSTSTGT, "evfststgt", MISC, spe_evfststgt) -BU_SPE_P (EVFSTSTLT, "evfststlt", MISC, spe_evfststlt) - -/* SPE evsel builtins. */ -BU_SPE_E (EVSEL_CMPGTS, "evsel_gts", MISC, spe_evcmpgts) -BU_SPE_E (EVSEL_CMPGTU, "evsel_gtu", MISC, spe_evcmpgtu) -BU_SPE_E (EVSEL_CMPLTS, "evsel_lts", MISC, spe_evcmplts) -BU_SPE_E (EVSEL_CMPLTU, "evsel_ltu", MISC, spe_evcmpltu) -BU_SPE_E (EVSEL_CMPEQ, "evsel_eq", MISC, spe_evcmpeq) -BU_SPE_E (EVSEL_FSCMPGT, "evsel_fsgt", MISC, spe_evfscmpgt) -BU_SPE_E (EVSEL_FSCMPLT, "evsel_fslt", MISC, spe_evfscmplt) -BU_SPE_E (EVSEL_FSCMPEQ, "evsel_fseq", MISC, spe_evfscmpeq) -BU_SPE_E (EVSEL_FSTSTGT, "evsel_fststgt", MISC, spe_evfststgt) -BU_SPE_E (EVSEL_FSTSTLT, "evsel_fststlt", MISC, spe_evfststlt) -BU_SPE_E (EVSEL_FSTSTEQ, "evsel_fststeq", MISC, spe_evfststeq) - -BU_SPE_1 (EVABS, "evabs", CONST, absv2si2) -BU_SPE_1 (EVADDSMIAAW, "evaddsmiaaw", CONST, spe_evaddsmiaaw) -BU_SPE_1 (EVADDSSIAAW, "evaddssiaaw", CONST, spe_evaddssiaaw) -BU_SPE_1 (EVADDUMIAAW, "evaddumiaaw", CONST, spe_evaddumiaaw) -BU_SPE_1 (EVADDUSIAAW, "evaddusiaaw", CONST, spe_evaddusiaaw) -BU_SPE_1 (EVCNTLSW, "evcntlsw", CONST, spe_evcntlsw) -BU_SPE_1 (EVCNTLZW, "evcntlzw", CONST, spe_evcntlzw) -BU_SPE_1 (EVEXTSB, "evextsb", CONST, spe_evextsb) -BU_SPE_1 (EVEXTSH, "evextsh", CONST, spe_evextsh) -BU_SPE_1 (EVFSABS, "evfsabs", CONST, spe_evfsabs) -BU_SPE_1 (EVFSCFSF, "evfscfsf", CONST, spe_evfscfsf) -BU_SPE_1 (EVFSCFSI, "evfscfsi", CONST, spe_evfscfsi) -BU_SPE_1 (EVFSCFUF, "evfscfuf", CONST, spe_evfscfuf) -BU_SPE_1 (EVFSCFUI, "evfscfui", CONST, spe_evfscfui) -BU_SPE_1 (EVFSCTSF, "evfsctsf", CONST, spe_evfsctsf) -BU_SPE_1 (EVFSCTSI, "evfsctsi", CONST, spe_evfsctsi) -BU_SPE_1 (EVFSCTSIZ, "evfsctsiz", CONST, spe_evfsctsiz) -BU_SPE_1 (EVFSCTUF, "evfsctuf", CONST, spe_evfsctuf) -BU_SPE_1 (EVFSCTUI, "evfsctui", CONST, spe_evfsctui) -BU_SPE_1 (EVFSCTUIZ, "evfsctuiz", CONST, spe_evfsctuiz) -BU_SPE_1 (EVFSNABS, "evfsnabs", CONST, spe_evfsnabs) -BU_SPE_1 (EVFSNEG, "evfsneg", CONST, spe_evfsneg) -BU_SPE_1 (EVMRA, "evmra", CONST, spe_evmra) -BU_SPE_1 (EVNEG, "evneg", CONST, negv2si2) -BU_SPE_1 (EVRNDW, "evrndw", CONST, spe_evrndw) -BU_SPE_1 (EVSUBFSMIAAW, "evsubfsmiaaw", CONST, spe_evsubfsmiaaw) -BU_SPE_1 (EVSUBFSSIAAW, "evsubfssiaaw", CONST, spe_evsubfssiaaw) -BU_SPE_1 (EVSUBFUMIAAW, "evsubfumiaaw", CONST, spe_evsubfumiaaw) -BU_SPE_1 (EVSUBFUSIAAW, "evsubfusiaaw", CONST, spe_evsubfusiaaw) - -/* SPE builtins that are handled as special cases. */ -BU_SPE_X (EVLDD, "evldd", MISC) -BU_SPE_X (EVLDDX, "evlddx", MISC) -BU_SPE_X (EVLDH, "evldh", MISC) -BU_SPE_X (EVLDHX, "evldhx", MISC) -BU_SPE_X (EVLDW, "evldw", MISC) -BU_SPE_X (EVLDWX, "evldwx", MISC) -BU_SPE_X (EVLHHESPLAT, "evlhhesplat", MISC) -BU_SPE_X (EVLHHESPLATX, "evlhhesplatx", MISC) -BU_SPE_X (EVLHHOSSPLAT, "evlhhossplat", MISC) -BU_SPE_X (EVLHHOSSPLATX, "evlhhossplatx", MISC) -BU_SPE_X (EVLHHOUSPLAT, "evlhhousplat", MISC) -BU_SPE_X (EVLHHOUSPLATX, "evlhhousplatx", MISC) -BU_SPE_X (EVLWHE, "evlwhe", MISC) -BU_SPE_X (EVLWHEX, "evlwhex", MISC) -BU_SPE_X (EVLWHOS, "evlwhos", MISC) -BU_SPE_X (EVLWHOSX, "evlwhosx", MISC) -BU_SPE_X (EVLWHOU, "evlwhou", MISC) -BU_SPE_X (EVLWHOUX, "evlwhoux", MISC) -BU_SPE_X (EVLWHSPLAT, "evlwhsplat", MISC) -BU_SPE_X (EVLWHSPLATX, "evlwhsplatx", MISC) -BU_SPE_X (EVLWWSPLAT, "evlwwsplat", MISC) -BU_SPE_X (EVLWWSPLATX, "evlwwsplatx", MISC) -BU_SPE_X (EVSPLATFI, "evsplatfi", MISC) -BU_SPE_X (EVSPLATI, "evsplati", MISC) -BU_SPE_X (EVSTDD, "evstdd", MISC) -BU_SPE_X (EVSTDDX, "evstddx", MISC) -BU_SPE_X (EVSTDH, "evstdh", MISC) -BU_SPE_X (EVSTDHX, "evstdhx", MISC) -BU_SPE_X (EVSTDW, "evstdw", MISC) -BU_SPE_X (EVSTDWX, "evstdwx", MISC) -BU_SPE_X (EVSTWHE, "evstwhe", MISC) -BU_SPE_X (EVSTWHEX, "evstwhex", MISC) -BU_SPE_X (EVSTWHO, "evstwho", MISC) -BU_SPE_X (EVSTWHOX, "evstwhox", MISC) -BU_SPE_X (EVSTWWE, "evstwwe", MISC) -BU_SPE_X (EVSTWWEX, "evstwwex", MISC) -BU_SPE_X (EVSTWWO, "evstwwo", MISC) -BU_SPE_X (EVSTWWOX, "evstwwox", MISC) -BU_SPE_X (MFSPEFSCR, "mfspefscr", MISC) -BU_SPE_X (MTSPEFSCR, "mtspefscr", MISC) - /* Power7 builtins, that aren't VSX instructions. */ BU_SPECIAL_X (POWER7_BUILTIN_BPERMD, "__builtin_bpermd", RS6000_BTM_POPCNTD, diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 3dc22237a79..230c2b4d311 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -611,10 +611,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_SF__"); /* options from the builtin masks. */ - /* Note that RS6000_BTM_SPE is enabled only if TARGET_SPE - (e.g. -mspe). */ - if ((bu_mask & RS6000_BTM_SPE) != 0) - rs6000_define_or_undefine_macro (define_p, "__SPE__"); /* Note that RS6000_BTM_PAIRED is enabled only if TARGET_PAIRED_FLOAT is enabled (e.g. -mpaired). */ if ((bu_mask & RS6000_BTM_PAIRED) != 0) diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 2955d971c28..8a231f5166c 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -41,7 +41,6 @@ extern int small_data_operand (rtx, machine_mode); extern bool mem_operand_gpr (rtx, machine_mode); extern bool mem_operand_ds_form (rtx, machine_mode); extern bool toc_relative_expr_p (const_rtx, bool); -extern bool invalid_e500_subreg (rtx, machine_mode); extern void validate_condition_mode (enum rtx_code, machine_mode); extern bool legitimate_constant_pool_address_p (const_rtx, machine_mode, bool); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 23e08ca531d..ac5e2de5398 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -108,7 +108,6 @@ typedef struct rs6000_stack { int lr_save_offset; /* offset to save LR from initial SP */ int cr_save_offset; /* offset to save CR from initial SP */ int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ - int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ int varargs_save_offset; /* offset to save the varargs registers */ int ehrd_offset; /* offset to EH return data */ int ehcr_offset; /* offset to EH CR field data */ @@ -123,10 +122,7 @@ typedef struct rs6000_stack { int cr_size; /* size to hold CR if not in fixed area */ int vrsave_size; /* size to hold VRSAVE */ int altivec_padding_size; /* size of altivec alignment padding */ - int spe_gp_size; /* size of 64-bit GPR save size for SPE */ - int spe_padding_size; HOST_WIDE_INT total_size; /* total bytes allocated for stack */ - int spe_64bit_regs_used; int savres_strategy; } rs6000_stack_t; @@ -134,8 +130,6 @@ typedef struct rs6000_stack { This is added to the cfun structure. */ typedef struct GTY(()) machine_function { - /* Whether the instruction chain has been scanned already. */ - int spe_insn_chain_scanned_p; /* Flags if __builtin_return_address (n) with n >= 1 was used. */ int ra_needs_full_frame; /* Flags if __builtin_return_address (0) was used. */ @@ -1278,11 +1272,9 @@ struct processor_costs ppca2_cost = { #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \ @@ -1303,9 +1295,6 @@ struct processor_costs ppca2_cost = { #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \ { NAME, ICODE, MASK, ATTR }, -#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \ - { NAME, ICODE, MASK, ATTR }, - #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \ { NAME, ICODE, MASK, ATTR }, @@ -1315,9 +1304,6 @@ struct processor_costs ppca2_cost = { #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \ { NAME, ICODE, MASK, ATTR }, -#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \ - { NAME, ICODE, MASK, ATTR }, - #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \ { NAME, ICODE, MASK, ATTR }, @@ -1339,11 +1325,9 @@ static const struct rs6000_builtin_info_type rs6000_builtin_info[] = #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X /* Support for -mveclibabi= to control which vector library to use. */ @@ -1351,7 +1335,6 @@ static tree (*rs6000_veclib_handler) (combined_fn, tree, tree); static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool); -static bool spe_func_has_64bit_regs_p (void); static struct machine_function * rs6000_init_machine_status (void); static int rs6000_ra_ever_killed (void); static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *); @@ -1381,10 +1364,7 @@ static tree builtin_function_type (machine_mode, machine_mode, static void rs6000_common_init_builtins (void); static void paired_init_builtins (void); static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx); -static void spe_init_builtins (void); static void htm_init_builtins (void); -static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); -static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); static rs6000_stack_t *rs6000_stack_info (void); static void is_altivec_return_reg (rtx, void *); @@ -1799,15 +1779,9 @@ static const struct attribute_spec rs6000_attribute_table[] = #undef TARGET_ADDRESS_COST #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0 -#undef TARGET_DWARF_REGISTER_SPAN -#define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span - #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra -#undef TARGET_MEMBER_TYPE_FORCES_BLK -#define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk - #undef TARGET_PROMOTE_FUNCTION_MODE #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode @@ -2076,9 +2050,6 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD); - else if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) - reg_size = UNITS_PER_SPE_WORD; - else if (ALTIVEC_REGNO_P (regno)) reg_size = UNITS_PER_ALTIVEC_WORD; @@ -2181,10 +2152,6 @@ rs6000_hard_regno_mode_ok (int regno, machine_mode mode) return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) || mode == V1TImode); - /* ...but GPRs can hold SIMD data on the SPE in one register. */ - if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) - return 1; - /* We cannot put non-VSX TImode or PTImode anywhere except general register and it must be able to fit within the register set. */ @@ -2835,9 +2802,6 @@ rs6000_debug_reg_global (void) if (rs6000_altivec_abi) fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true"); - if (rs6000_spe_abi) - fprintf (stderr, DEBUG_FMT_S, "spe_abi", "true"); - if (rs6000_darwin64_abi) fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true"); @@ -3897,7 +3861,6 @@ rs6000_builtin_mask_calculate (void) return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0) | ((TARGET_VSX) ? RS6000_BTM_VSX : 0) - | ((TARGET_SPE) ? RS6000_BTM_SPE : 0) | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0) | ((TARGET_FRE) ? RS6000_BTM_FRE : 0) | ((TARGET_FRES) ? RS6000_BTM_FRES : 0) @@ -4234,26 +4197,15 @@ rs6000_option_override_internal (bool global_init_p) (rs6000_cpu == PROCESSOR_PPC8540 || rs6000_cpu == PROCESSOR_PPC8548); - if (!global_options_set.x_rs6000_spe_abi) - rs6000_spe_abi = spe_capable_cpu; - if (!global_options_set.x_rs6000_spe) rs6000_spe = spe_capable_cpu; } - if (global_options_set.x_rs6000_spe_abi - && rs6000_spe_abi - && !TARGET_SPE_ABI) - error ("not configured for SPE ABI"); - - if (global_options_set.x_rs6000_spe - && rs6000_spe - && !TARGET_SPE) + if (global_options_set.x_rs6000_spe && rs6000_spe) error ("not configured for SPE instruction set"); if (main_target_opt != NULL - && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi) - || (main_target_opt->x_rs6000_spe != rs6000_spe))) + && main_target_opt->x_rs6000_spe != rs6000_spe) error ("target attribute or pragma changes SPE ABI"); if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3 @@ -4262,13 +4214,6 @@ rs6000_option_override_internal (bool global_init_p) { if (TARGET_ALTIVEC) error ("AltiVec not supported in this target"); - if (TARGET_SPE) - error ("SPE not supported in this target"); - } - if (rs6000_cpu == PROCESSOR_PPCE6500) - { - if (TARGET_SPE) - error ("SPE not supported in this target"); } /* If we are optimizing big endian systems for space, use the load/store @@ -5902,15 +5847,6 @@ rs6000_preferred_simd_mode (machine_mode mode) return V16QImode; default:; } - if (TARGET_SPE) - switch (mode) - { - case SFmode: - return V2SFmode; - case SImode: - return V2SImode; - default:; - } if (TARGET_PAIRED_FLOAT && mode == SFmode) return V2SFmode; @@ -7015,7 +6951,7 @@ xxspltib_constant_p (rtx op, const char * output_vec_const_move (rtx *operands) { - int cst, cst2, shift; + int shift; machine_mode mode; rtx dest, vec; @@ -7107,23 +7043,7 @@ output_vec_const_move (rtx *operands) } } - gcc_assert (TARGET_SPE); - - /* Vector constant 0 is handled as a splitter of V2SI, and in the - pattern of V1DI, V4HI, and V2SF. - - FIXME: We should probably return # and add post reload - splitters for these, but this way is so easy ;-). */ - cst = INTVAL (CONST_VECTOR_ELT (vec, 0)); - cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1)); - operands[1] = CONST_VECTOR_ELT (vec, 0); - operands[2] = CONST_VECTOR_ELT (vec, 1); - if (cst == cst2) - return "li %0,%1\n\tevmergelo %0,%0,%0"; - else if (WORDS_BIG_ENDIAN) - return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; - else - return "li %0,%2\n\tevmergelo %0,%0,%0\n\tli %0,%1"; + gcc_unreachable (); } /* Initialize TARGET of vector PAIRED to VALS. */ @@ -8195,21 +8115,6 @@ rs6000_split_v4si_init (rtx operands[]) gcc_unreachable (); } -/* Return TRUE if OP is an invalid SUBREG operation on the e500. */ - -bool -invalid_e500_subreg (rtx op, machine_mode mode) -{ - if (TARGET_SPE - && GET_CODE (op) == SUBREG - && mode == SImode - && REG_P (SUBREG_REG (op)) - && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op)))) - return true; - - return false; -} - /* Return alignment of TYPE. Existing alignment is ALIGN. HOW selects whether the alignment is abi mandated, optional, or both abi and optional alignment. */ @@ -8221,8 +8126,7 @@ rs6000_data_alignment (tree type, unsigned int align, enum data_align how) { if (TREE_CODE (type) == VECTOR_TYPE) { - if ((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (type))) - || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type)))) + if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type))) { if (align < 64) align = 64; @@ -8347,13 +8251,6 @@ small_data_operand (rtx op ATTRIBUTE_UNUSED, if (DEFAULT_ABI != ABI_V4) return 0; - /* Vector and float memory instructions have a limited offset on the - SPE, so using a vector or float variable directly as an operand is - not useful. */ - if (TARGET_SPE - && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode))) - return 0; - if (GET_CODE (op) == SYMBOL_REF) sym_ref = op; @@ -9106,7 +9003,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, && GET_CODE (XEXP (x, 1)) == CONST_INT && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000 - extra) - && !SPE_VECTOR_MODE (mode)) + && !PAIRED_VECTOR_MODE (mode)) { HOST_WIDE_INT high_int, low_int; rtx sum; @@ -9131,11 +9028,11 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, return gen_rtx_PLUS (Pmode, XEXP (x, 0), force_reg (Pmode, force_operand (XEXP (x, 1), 0))); } - else if (SPE_VECTOR_MODE (mode)) + else if (PAIRED_VECTOR_MODE (mode)) { if (mode == DImode) return x; - /* We accept [reg + reg] and [reg + OFFSET]. */ + /* We accept [reg + reg]. */ if (GET_CODE (x) == PLUS) { @@ -9144,13 +9041,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, rtx y; op1 = force_reg (Pmode, op1); - - if (GET_CODE (op2) != REG - && (GET_CODE (op2) != CONST_INT - || !SPE_CONST_OFFSET_OK (INTVAL (op2)) - || (GET_MODE_SIZE (mode) > 8 - && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8)))) - op2 = force_reg (Pmode, op2); + op2 = force_reg (Pmode, op2); /* We can't always do [reg + reg] for these, because [reg + reg + offset] is not a legitimate addressing mode. */ @@ -9894,7 +9785,7 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode, && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1) && CONST_INT_P (XEXP (x, 1)) && reg_offset_p - && !SPE_VECTOR_MODE (mode) + && !PAIRED_VECTOR_MODE (mode) && (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))) { HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); @@ -9935,7 +9826,7 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode, && reg_offset_p && !quad_offset_p && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)) - && !SPE_VECTOR_MODE (mode) + && !PAIRED_VECTOR_MODE (mode) #if TARGET_MACHO && DEFAULT_ABI == ABI_DARWIN && (flag_pic || MACHO_DYNAMIC_NO_PIC_P) @@ -10409,20 +10300,6 @@ rs6000_conditional_register_usage (void) fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; - if (TARGET_SPE) - { - global_regs[SPEFSCR_REGNO] = 1; - /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit - registers in prologues and epilogues. We no longer use r14 - for FIXED_SCRATCH, but we're keeping r14 out of the allocation - pool for link-compatibility with older versions of GCC. Once - "old" code has died out, we can return r14 to the allocation - pool. */ - fixed_regs[14] - = call_used_regs[14] - = call_really_used_regs[14] = 1; - } - if (!TARGET_ALTIVEC && !TARGET_VSX) { for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) @@ -11326,25 +11203,6 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode) emit_set: emit_insn (gen_rtx_SET (operands[0], operands[1])); } - -/* Return true if a structure, union or array containing FIELD should be - accessed using `BLKMODE'. - - For the SPE, simd types are V2SI, and gcc can be tempted to put the - entire thing in a DI and use subregs to access the internals. - store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the - back-end. Because a single GPR can hold a V2SI, but not a DI, the - best thing to do is set structs to BLKmode and avoid Severe Tire - Damage. - - On e500 v2, DF and DI modes suffer from the same anomaly. DF can - fit into 1, whereas DI still needs two. */ - -static bool -rs6000_member_type_forces_blk (const_tree field, machine_mode) -{ - return (TARGET_SPE && TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE); -} /* Nonzero if we can use a floating-point register to pass this arg. */ #define USE_FP_FOR_ARG_P(CUM,MODE) \ @@ -11803,7 +11661,7 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rs6000_passes_long_double = true; } if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode) - || SPE_VECTOR_MODE (return_mode)) + || PAIRED_VECTOR_MODE (return_mode)) rs6000_passes_vector = true; } } @@ -11981,7 +11839,7 @@ rs6000_function_arg_boundary (machine_mode mode, const_tree type) return 64; else if (FLOAT128_VECTOR_P (mode)) return 128; - else if (SPE_VECTOR_MODE (mode) + else if (PAIRED_VECTOR_MODE (mode) || (type && TREE_CODE (type) == VECTOR_TYPE && int_size_in_bytes (type) >= 8 && int_size_in_bytes (type) < 16)) @@ -12263,7 +12121,7 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode, rs6000_passes_long_double = true; } if ((named && ALTIVEC_OR_VSX_VECTOR_MODE (mode)) - || (SPE_VECTOR_MODE (mode) + || (PAIRED_VECTOR_MODE (mode) && !cum->stdarg && cum->sysv_gregno <= GP_ARG_MAX_REG)) rs6000_passes_vector = true; @@ -12322,11 +12180,6 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode, } } } - else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) - && !cum->stdarg - && cum->sysv_gregno <= GP_ARG_MAX_REG) - cum->sysv_gregno++; - else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type)) { int size = int_size_in_bytes (type); @@ -12458,44 +12311,6 @@ rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode, 0); } -/* Determine where to put a SIMD argument on the SPE. */ -static rtx -rs6000_spe_function_arg (const CUMULATIVE_ARGS *cum, machine_mode mode, - const_tree type) -{ - int gregno = cum->sysv_gregno; - - if (cum->stdarg) - { - int n_words = rs6000_arg_size (mode, type); - - /* SPE vectors are put in odd registers. */ - if (n_words == 2 && (gregno & 1) == 0) - gregno += 1; - - if (gregno + n_words - 1 <= GP_ARG_MAX_REG) - { - rtx r1, r2; - machine_mode m = SImode; - - r1 = gen_rtx_REG (m, gregno); - r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); - r2 = gen_rtx_REG (m, gregno + 1); - r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); - return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); - } - else - return NULL_RTX; - } - else - { - if (gregno <= GP_ARG_MAX_REG) - return gen_rtx_REG (mode, gregno); - else - return NULL_RTX; - } -} - /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the structure between cum->intoffset and bitpos to integer registers. */ @@ -12862,17 +12677,12 @@ rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode, && (cum->call_cookie & CALL_LIBCALL) == 0 && (cum->stdarg || (cum->nargs_prototype < 0 - && (cum->prototype || TARGET_NO_PROTOTYPE)))) - { - /* For the SPE, we need to crxor CR6 always. */ - if (TARGET_SPE_ABI) - return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); - else if (TARGET_HARD_FLOAT) - return GEN_INT (cum->call_cookie - | ((cum->fregno == FP_ARG_MIN_REG) - ? CALL_V4_SET_FP_ARGS - : CALL_V4_CLEAR_FP_ARGS)); - } + && (cum->prototype || TARGET_NO_PROTOTYPE))) + && TARGET_HARD_FLOAT) + return GEN_INT (cum->call_cookie + | ((cum->fregno == FP_ARG_MIN_REG) + ? CALL_V4_SET_FP_ARGS + : CALL_V4_CLEAR_FP_ARGS)); return GEN_INT (cum->call_cookie & ~CALL_LIBCALL); } @@ -12957,8 +12767,6 @@ rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode, return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words); } } - else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)) - return rs6000_spe_function_arg (cum, mode, type); else if (abi == ABI_V4) { @@ -14100,11 +13908,9 @@ def_builtin (const char *name, tree type, enum rs6000_builtins code) #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) @@ -14115,11 +13921,9 @@ def_builtin (const char *name, tree type, enum rs6000_builtins code) #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) static const struct builtin_description bdesc_3arg[] = @@ -14135,11 +13939,9 @@ static const struct builtin_description bdesc_3arg[] = #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) @@ -14150,11 +13952,9 @@ static const struct builtin_description bdesc_3arg[] = #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \ { MASK, ICODE, NAME, ENUM }, -#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) static const struct builtin_description bdesc_dst[] = @@ -14170,11 +13970,9 @@ static const struct builtin_description bdesc_dst[] = #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) @@ -14185,11 +13983,9 @@ static const struct builtin_description bdesc_dst[] = #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) static const struct builtin_description bdesc_2arg[] = @@ -14203,11 +13999,9 @@ static const struct builtin_description bdesc_2arg[] = #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) @@ -14216,13 +14010,11 @@ static const struct builtin_description bdesc_2arg[] = #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \ { MASK, ICODE, NAME, ENUM }, #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) /* AltiVec predicates. */ @@ -14232,74 +14024,6 @@ static const struct builtin_description bdesc_altivec_preds[] = #include "rs6000-builtin.def" }; -/* SPE predicates. */ -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S -#undef RS6000_BUILTIN_X - -#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \ - { MASK, ICODE, NAME, ENUM }, - -#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) - -static const struct builtin_description bdesc_spe_predicates[] = -{ -#include "rs6000-builtin.def" -}; - -/* SPE evsel predicates. */ -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S -#undef RS6000_BUILTIN_X - -#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \ - { MASK, ICODE, NAME, ENUM }, - -#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) - -static const struct builtin_description bdesc_spe_evsel[] = -{ -#include "rs6000-builtin.def" -}; - /* PAIRED predicates. */ #undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 @@ -14307,11 +14031,9 @@ static const struct builtin_description bdesc_spe_evsel[] = #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) @@ -14320,13 +14042,11 @@ static const struct builtin_description bdesc_spe_evsel[] = #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \ { MASK, ICODE, NAME, ENUM }, -#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) static const struct builtin_description bdesc_paired_preds[] = @@ -14342,11 +14062,9 @@ static const struct builtin_description bdesc_paired_preds[] = #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) @@ -14357,11 +14075,9 @@ static const struct builtin_description bdesc_paired_preds[] = { MASK, ICODE, NAME, ENUM }, #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) static const struct builtin_description bdesc_abs[] = @@ -14378,11 +14094,9 @@ static const struct builtin_description bdesc_abs[] = #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) @@ -14393,11 +14107,9 @@ static const struct builtin_description bdesc_abs[] = #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) static const struct builtin_description bdesc_1arg[] = @@ -14413,11 +14125,9 @@ static const struct builtin_description bdesc_1arg[] = #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \ @@ -14428,11 +14138,9 @@ static const struct builtin_description bdesc_1arg[] = #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) static const struct builtin_description bdesc_0arg[] = @@ -14447,11 +14155,9 @@ static const struct builtin_description bdesc_0arg[] = #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) @@ -14460,13 +14166,11 @@ static const struct builtin_description bdesc_0arg[] = #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \ { MASK, ICODE, NAME, ENUM }, #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) static const struct builtin_description bdesc_htm[] = @@ -14480,11 +14184,9 @@ static const struct builtin_description bdesc_htm[] = #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S /* Return true if a builtin function is overloaded. */ bool @@ -14584,9 +14286,7 @@ rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target) if (icode == CODE_FOR_altivec_vspltisb || icode == CODE_FOR_altivec_vspltish - || icode == CODE_FOR_altivec_vspltisw - || icode == CODE_FOR_spe_evsplatfi - || icode == CODE_FOR_spe_evsplati) + || icode == CODE_FOR_altivec_vspltisw) { /* Only allow 5-bit *signed* literals. */ if (GET_CODE (op0) != CONST_INT @@ -14672,24 +14372,7 @@ rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target) || icode == CODE_FOR_altivec_vctuxs || icode == CODE_FOR_altivec_vspltb || icode == CODE_FOR_altivec_vsplth - || icode == CODE_FOR_altivec_vspltw - || icode == CODE_FOR_spe_evaddiw - || icode == CODE_FOR_spe_evldd - || icode == CODE_FOR_spe_evldh - || icode == CODE_FOR_spe_evldw - || icode == CODE_FOR_spe_evlhhesplat - || icode == CODE_FOR_spe_evlhhossplat - || icode == CODE_FOR_spe_evlhhousplat - || icode == CODE_FOR_spe_evlwhe - || icode == CODE_FOR_spe_evlwhos - || icode == CODE_FOR_spe_evlwhou - || icode == CODE_FOR_spe_evlwhsplat - || icode == CODE_FOR_spe_evlwwsplat - || icode == CODE_FOR_spe_evrlwi - || icode == CODE_FOR_spe_evslwi - || icode == CODE_FOR_spe_evsrwis - || icode == CODE_FOR_spe_evsubifw - || icode == CODE_FOR_spe_evsrwiu) + || icode == CODE_FOR_altivec_vspltw) { /* Only allow 5-bit unsigned literals. */ STRIP_NOPS (arg1); @@ -15054,39 +14737,6 @@ altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk) return target; } -static rtx -spe_expand_stv_builtin (enum insn_code icode, tree exp) -{ - tree arg0 = CALL_EXPR_ARG (exp, 0); - tree arg1 = CALL_EXPR_ARG (exp, 1); - tree arg2 = CALL_EXPR_ARG (exp, 2); - rtx op0 = expand_normal (arg0); - rtx op1 = expand_normal (arg1); - rtx op2 = expand_normal (arg2); - rtx pat; - machine_mode mode0 = insn_data[icode].operand[0].mode; - machine_mode mode1 = insn_data[icode].operand[1].mode; - machine_mode mode2 = insn_data[icode].operand[2].mode; - - /* Invalid arguments. Bail before doing anything stoopid! */ - if (arg0 == error_mark_node - || arg1 == error_mark_node - || arg2 == error_mark_node) - return const0_rtx; - - if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) - op0 = copy_to_mode_reg (mode2, op0); - if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) - op1 = copy_to_mode_reg (mode0, op1); - if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) - op2 = copy_to_mode_reg (mode1, op2); - - pat = GEN_FCN (icode) (op1, op2, op0); - if (pat) - emit_insn (pat); - return NULL_RTX; -} - static rtx paired_expand_stv_builtin (enum insn_code icode, tree exp) { @@ -16511,171 +16161,6 @@ paired_expand_builtin (tree exp, rtx target, bool * expandedp) return NULL_RTX; } -/* Binops that need to be initialized manually, but can be expanded - automagically by rs6000_expand_binop_builtin. */ -static const struct builtin_description bdesc_2arg_spe[] = -{ - { RS6000_BTM_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } -}; - -/* Expand the builtin in EXP and store the result in TARGET. Store - true in *EXPANDEDP if we found a builtin to expand. - - This expands the SPE builtins that are not simple unary and binary - operations. */ -static rtx -spe_expand_builtin (tree exp, rtx target, bool *expandedp) -{ - tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - tree arg1, arg0; - enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl); - enum insn_code icode; - machine_mode tmode, mode0; - rtx pat, op0; - const struct builtin_description *d; - size_t i; - - *expandedp = true; - - /* Syntax check for a 5-bit unsigned immediate. */ - switch (fcode) - { - case SPE_BUILTIN_EVSTDD: - case SPE_BUILTIN_EVSTDH: - case SPE_BUILTIN_EVSTDW: - case SPE_BUILTIN_EVSTWHE: - case SPE_BUILTIN_EVSTWHO: - case SPE_BUILTIN_EVSTWWE: - case SPE_BUILTIN_EVSTWWO: - arg1 = CALL_EXPR_ARG (exp, 2); - if (TREE_CODE (arg1) != INTEGER_CST - || TREE_INT_CST_LOW (arg1) & ~0x1f) - { - error ("argument 2 must be a 5-bit unsigned literal"); - return const0_rtx; - } - break; - default: - break; - } - - /* The evsplat*i instructions are not quite generic. */ - switch (fcode) - { - case SPE_BUILTIN_EVSPLATFI: - return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi, - exp, target); - case SPE_BUILTIN_EVSPLATI: - return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati, - exp, target); - default: - break; - } - - d = bdesc_2arg_spe; - for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) - if (d->code == fcode) - return rs6000_expand_binop_builtin (d->icode, exp, target); - - d = bdesc_spe_predicates; - for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) - if (d->code == fcode) - return spe_expand_predicate_builtin (d->icode, exp, target); - - d = bdesc_spe_evsel; - for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) - if (d->code == fcode) - return spe_expand_evsel_builtin (d->icode, exp, target); - - switch (fcode) - { - case SPE_BUILTIN_EVSTDDX: - return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp); - case SPE_BUILTIN_EVSTDHX: - return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp); - case SPE_BUILTIN_EVSTDWX: - return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp); - case SPE_BUILTIN_EVSTWHEX: - return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp); - case SPE_BUILTIN_EVSTWHOX: - return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp); - case SPE_BUILTIN_EVSTWWEX: - return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp); - case SPE_BUILTIN_EVSTWWOX: - return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp); - case SPE_BUILTIN_EVSTDD: - return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp); - case SPE_BUILTIN_EVSTDH: - return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp); - case SPE_BUILTIN_EVSTDW: - return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp); - case SPE_BUILTIN_EVSTWHE: - return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp); - case SPE_BUILTIN_EVSTWHO: - return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp); - case SPE_BUILTIN_EVSTWWE: - return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp); - case SPE_BUILTIN_EVSTWWO: - return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp); - case SPE_BUILTIN_MFSPEFSCR: - icode = CODE_FOR_spe_mfspefscr; - tmode = insn_data[icode].operand[0].mode; - - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - - pat = GEN_FCN (icode) (target); - if (! pat) - return 0; - emit_insn (pat); - return target; - case SPE_BUILTIN_MTSPEFSCR: - icode = CODE_FOR_spe_mtspefscr; - arg0 = CALL_EXPR_ARG (exp, 0); - op0 = expand_normal (arg0); - mode0 = insn_data[icode].operand[0].mode; - - if (arg0 == error_mark_node) - return const0_rtx; - - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - - pat = GEN_FCN (icode) (op0); - if (pat) - emit_insn (pat); - return NULL_RTX; - default: - break; - } - - *expandedp = false; - return NULL_RTX; -} - static rtx paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target) { @@ -16748,164 +16233,6 @@ paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target) return target; } -static rtx -spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target) -{ - rtx pat, scratch, tmp; - tree form = CALL_EXPR_ARG (exp, 0); - tree arg0 = CALL_EXPR_ARG (exp, 1); - tree arg1 = CALL_EXPR_ARG (exp, 2); - rtx op0 = expand_normal (arg0); - rtx op1 = expand_normal (arg1); - machine_mode mode0 = insn_data[icode].operand[1].mode; - machine_mode mode1 = insn_data[icode].operand[2].mode; - int form_int; - enum rtx_code code; - - if (TREE_CODE (form) != INTEGER_CST) - { - error ("argument 1 of __builtin_spe_predicate must be a constant"); - return const0_rtx; - } - else - form_int = TREE_INT_CST_LOW (form); - - gcc_assert (mode0 == mode1); - - if (arg0 == error_mark_node || arg1 == error_mark_node) - return const0_rtx; - - if (target == 0 - || GET_MODE (target) != SImode - || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) - target = gen_reg_rtx (SImode); - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - - scratch = gen_reg_rtx (CCmode); - - pat = GEN_FCN (icode) (scratch, op0, op1); - if (! pat) - return const0_rtx; - emit_insn (pat); - - /* There are 4 variants for each predicate: _any_, _all_, _upper_, - _lower_. We use one compare, but look in different bits of the - CR for each variant. - - There are 2 elements in each SPE simd type (upper/lower). The CR - bits are set as follows: - - BIT0 | BIT 1 | BIT 2 | BIT 3 - U | L | (U | L) | (U & L) - - So, for an "all" relationship, BIT 3 would be set. - For an "any" relationship, BIT 2 would be set. Etc. - - Following traditional nomenclature, these bits map to: - - BIT0 | BIT 1 | BIT 2 | BIT 3 - LT | GT | EQ | OV - - Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. - */ - - switch (form_int) - { - /* All variant. OV bit. */ - case 0: - /* We need to get to the OV bit, which is the ORDERED bit. We - could generate (ordered:SI (reg:CC xx) (const_int 0)), but - that's ugly and will make validate_condition_mode die. - So let's just use another pattern. */ - emit_insn (gen_move_from_CR_ov_bit (target, scratch)); - return target; - /* Any variant. EQ bit. */ - case 1: - code = EQ; - break; - /* Upper variant. LT bit. */ - case 2: - code = LT; - break; - /* Lower variant. GT bit. */ - case 3: - code = GT; - break; - default: - error ("argument 1 of __builtin_spe_predicate is out of range"); - return const0_rtx; - } - - tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); - emit_move_insn (target, tmp); - - return target; -} - -/* The evsel builtins look like this: - - e = __builtin_spe_evsel_OP (a, b, c, d); - - and work like this: - - e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; - e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; -*/ - -static rtx -spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target) -{ - rtx pat, scratch; - tree arg0 = CALL_EXPR_ARG (exp, 0); - tree arg1 = CALL_EXPR_ARG (exp, 1); - tree arg2 = CALL_EXPR_ARG (exp, 2); - tree arg3 = CALL_EXPR_ARG (exp, 3); - rtx op0 = expand_normal (arg0); - rtx op1 = expand_normal (arg1); - rtx op2 = expand_normal (arg2); - rtx op3 = expand_normal (arg3); - machine_mode mode0 = insn_data[icode].operand[1].mode; - machine_mode mode1 = insn_data[icode].operand[2].mode; - - gcc_assert (mode0 == mode1); - - if (arg0 == error_mark_node || arg1 == error_mark_node - || arg2 == error_mark_node || arg3 == error_mark_node) - return const0_rtx; - - if (target == 0 - || GET_MODE (target) != mode0 - || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) - target = gen_reg_rtx (mode0); - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode0, op1); - if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) - op2 = copy_to_mode_reg (mode0, op2); - if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) - op3 = copy_to_mode_reg (mode0, op3); - - /* Generate the compare. */ - scratch = gen_reg_rtx (CCmode); - pat = GEN_FCN (icode) (scratch, op0, op1); - if (! pat) - return const0_rtx; - emit_insn (pat); - - if (mode0 == V2SImode) - emit_insn (gen_spe_evsel (target, op2, op3, scratch)); - else - emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); - - return target; -} - /* Raise an error message for a builtin function that is called without the appropriate target options being set. */ @@ -16927,8 +16254,6 @@ rs6000_invalid_builtin (enum rs6000_builtins fncode) error ("Builtin function %s requires the -maltivec option", name); else if ((fnmask & RS6000_BTM_PAIRED) != 0) error ("Builtin function %s requires the -mpaired option", name); - else if ((fnmask & RS6000_BTM_SPE) != 0) - error ("Builtin function %s requires the -mspe option", name); else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR)) == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR)) error ("Builtin function %s requires the -mhard-dfp and" @@ -17451,13 +16776,6 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, { ret = altivec_expand_builtin (exp, target, &success); - if (success) - return ret; - } - if (TARGET_SPE) - { - ret = spe_expand_builtin (exp, target, &success); - if (success) return ret; } @@ -17534,9 +16852,8 @@ rs6000_init_builtins (void) machine_mode mode; if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_init_builtins%s%s%s%s\n", + fprintf (stderr, "rs6000_init_builtins%s%s%s\n", (TARGET_PAIRED_FLOAT) ? ", paired" : "", - (TARGET_SPE) ? ", spe" : "", (TARGET_ALTIVEC) ? ", altivec" : "", (TARGET_VSX) ? ", vsx" : ""); @@ -17735,14 +17052,12 @@ rs6000_init_builtins (void) use of the target attribute. */ if (TARGET_PAIRED_FLOAT) paired_init_builtins (); - if (TARGET_SPE) - spe_init_builtins (); if (TARGET_EXTRA_BUILTINS) altivec_init_builtins (); if (TARGET_HTM) htm_init_builtins (); - if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT) + if (TARGET_EXTRA_BUILTINS || TARGET_PAIRED_FLOAT) rs6000_common_init_builtins (); ftype = build_function_type_list (ieee128_float_type_node, @@ -17833,214 +17148,6 @@ rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) return rs6000_builtin_decls[code]; } -static void -spe_init_builtins (void) -{ - tree puint_type_node = build_pointer_type (unsigned_type_node); - tree pushort_type_node = build_pointer_type (short_unsigned_type_node); - const struct builtin_description *d; - size_t i; - HOST_WIDE_INT builtin_mask = rs6000_builtin_mask; - - tree v2si_ftype_4_v2si - = build_function_type_list (opaque_V2SI_type_node, - opaque_V2SI_type_node, - opaque_V2SI_type_node, - opaque_V2SI_type_node, - opaque_V2SI_type_node, - NULL_TREE); - - tree v2sf_ftype_4_v2sf - = build_function_type_list (opaque_V2SF_type_node, - opaque_V2SF_type_node, - opaque_V2SF_type_node, - opaque_V2SF_type_node, - opaque_V2SF_type_node, - NULL_TREE); - - tree int_ftype_int_v2si_v2si - = build_function_type_list (integer_type_node, - integer_type_node, - opaque_V2SI_type_node, - opaque_V2SI_type_node, - NULL_TREE); - - tree int_ftype_int_v2sf_v2sf - = build_function_type_list (integer_type_node, - integer_type_node, - opaque_V2SF_type_node, - opaque_V2SF_type_node, - NULL_TREE); - - tree void_ftype_v2si_puint_int - = build_function_type_list (void_type_node, - opaque_V2SI_type_node, - puint_type_node, - integer_type_node, - NULL_TREE); - - tree void_ftype_v2si_puint_char - = build_function_type_list (void_type_node, - opaque_V2SI_type_node, - puint_type_node, - char_type_node, - NULL_TREE); - - tree void_ftype_v2si_pv2si_int - = build_function_type_list (void_type_node, - opaque_V2SI_type_node, - opaque_p_V2SI_type_node, - integer_type_node, - NULL_TREE); - - tree void_ftype_v2si_pv2si_char - = build_function_type_list (void_type_node, - opaque_V2SI_type_node, - opaque_p_V2SI_type_node, - char_type_node, - NULL_TREE); - - tree void_ftype_int - = build_function_type_list (void_type_node, integer_type_node, NULL_TREE); - - tree int_ftype_void - = build_function_type_list (integer_type_node, NULL_TREE); - - tree v2si_ftype_pv2si_int - = build_function_type_list (opaque_V2SI_type_node, - opaque_p_V2SI_type_node, - integer_type_node, - NULL_TREE); - - tree v2si_ftype_puint_int - = build_function_type_list (opaque_V2SI_type_node, - puint_type_node, - integer_type_node, - NULL_TREE); - - tree v2si_ftype_pushort_int - = build_function_type_list (opaque_V2SI_type_node, - pushort_type_node, - integer_type_node, - NULL_TREE); - - tree v2si_ftype_signed_char - = build_function_type_list (opaque_V2SI_type_node, - signed_char_type_node, - NULL_TREE); - - add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node); - - /* Initialize irregular SPE builtins. */ - - def_builtin ("__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); - def_builtin ("__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); - def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); - def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); - def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); - def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); - def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); - def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); - def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); - def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); - def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); - def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); - def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); - def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); - def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); - def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); - def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI); - def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI); - - /* Loads. */ - def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); - def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); - def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); - def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); - def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); - def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); - def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); - def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); - def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); - def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); - def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); - def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); - def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); - def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); - def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); - def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); - def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); - def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); - def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); - def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); - def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); - def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); - - /* Predicates. */ - d = bdesc_spe_predicates; - for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) - { - tree type; - HOST_WIDE_INT mask = d->mask; - - if ((mask & builtin_mask) != mask) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "spe_init_builtins, skip predicate %s\n", - d->name); - continue; - } - - /* Cannot define builtin if the instruction is disabled. */ - gcc_assert (d->icode != CODE_FOR_nothing); - switch (insn_data[d->icode].operand[1].mode) - { - case V2SImode: - type = int_ftype_int_v2si_v2si; - break; - case V2SFmode: - type = int_ftype_int_v2sf_v2sf; - break; - default: - gcc_unreachable (); - } - - def_builtin (d->name, type, d->code); - } - - /* Evsel predicates. */ - d = bdesc_spe_evsel; - for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) - { - tree type; - HOST_WIDE_INT mask = d->mask; - - if ((mask & builtin_mask) != mask) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "spe_init_builtins, skip evsel %s\n", - d->name); - continue; - } - - /* Cannot define builtin if the instruction is disabled. */ - gcc_assert (d->icode != CODE_FOR_nothing); - switch (insn_data[d->icode].operand[1].mode) - { - case V2SImode: - type = v2si_ftype_4_v2si; - break; - case V2SFmode: - type = v2sf_ftype_4_v2sf; - break; - default: - gcc_unreachable (); - } - - def_builtin (d->name, type, d->code); - } -} - static void paired_init_builtins (void) { @@ -19558,8 +18665,6 @@ expand_block_clear (rtx operands[]) clear_step = 16; else if (TARGET_POWERPC64 && (align >= 64 || !STRICT_ALIGNMENT)) clear_step = 8; - else if (TARGET_SPE && align >= 64) - clear_step = 8; else clear_step = 4; @@ -19578,11 +18683,6 @@ expand_block_clear (rtx operands[]) clear_bytes = 16; mode = V4SImode; } - else if (bytes >= 8 && TARGET_SPE && align >= 64) - { - clear_bytes = 8; - mode = V2SImode; - } else if (bytes >= 8 && TARGET_POWERPC64 && (align >= 64 || !STRICT_ALIGNMENT)) { @@ -20790,12 +19890,6 @@ expand_block_move (rtx operands[]) mode = V4SImode; gen_func.mov = gen_movv4si; } - else if (TARGET_SPE && bytes >= 8 && align >= 64) - { - move_bytes = 8; - mode = V2SImode; - gen_func.mov = gen_movv2si; - } else if (TARGET_STRING && bytes > 24 /* move up to 32 bytes at a time */ && ! fixed_regs[5] @@ -23223,10 +22317,6 @@ rs6000_cannot_change_mode_class (machine_mode from, && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1) return true; - if (TARGET_SPE && (SPE_VECTOR_MODE (from) + SPE_VECTOR_MODE (to)) == 1 - && reg_classes_intersect_p (GENERAL_REGS, rclass)) - return true; - return false; } @@ -24062,34 +23152,6 @@ print_operand (FILE *file, rtx x, int code) tmp = XEXP (x, 0); - /* Ugly hack because %y is overloaded. */ - if (TARGET_SPE - && (GET_MODE_SIZE (GET_MODE (x)) == 8 - || FLOAT128_2REG_P (GET_MODE (x)) - || GET_MODE (x) == TImode - || GET_MODE (x) == PTImode)) - { - /* Handle [reg]. */ - if (REG_P (tmp)) - { - fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); - break; - } - /* Handle [reg+UIMM]. */ - else if (GET_CODE (tmp) == PLUS && - GET_CODE (XEXP (tmp, 1)) == CONST_INT) - { - int x; - - gcc_assert (REG_P (XEXP (tmp, 0))); - - x = INTVAL (XEXP (tmp, 1)); - fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); - break; - } - - /* Fall through. Must be [reg+reg]. */ - } if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x)) && GET_CODE (tmp) == AND && GET_CODE (XEXP (tmp, 1)) == CONST_INT @@ -26922,13 +25984,6 @@ rs6000_savres_strategy (rs6000_stack_t *info, | SAVE_INLINE_GPRS | SAVE_INLINE_VRS); - /* Saving CR interferes with the exit routines used on the SPE, so - just punt here. */ - if (TARGET_SPE_ABI - && info->spe_64bit_regs_used - && info->cr_save_p) - strategy |= REST_INLINE_GPRS; - /* We can only use the out-of-line routines to restore fprs if we've saved all the registers from first_fp_reg_save in the prologue. Otherwise, we risk loading garbage. Of course, if we have saved @@ -26971,7 +26026,6 @@ rs6000_savres_strategy (rs6000_stack_t *info, if (TARGET_MULTIPLE && !TARGET_POWERPC64 - && !(TARGET_SPE_ABI && info->spe_64bit_regs_used) && info->first_gp_reg_save < 31 && !(flag_shrink_wrap && flag_shrink_wrap_separate @@ -27190,15 +26244,6 @@ rs6000_stack_info (void) memset (info, 0, sizeof (*info)); info->reload_completed = reload_completed; - if (TARGET_SPE) - { - /* Cache value so we don't rescan instruction chain over and over. */ - if (cfun->machine->spe_insn_chain_scanned_p == 0) - cfun->machine->spe_insn_chain_scanned_p - = spe_func_has_64bit_regs_p () + 1; - info->spe_64bit_regs_used = cfun->machine->spe_insn_chain_scanned_p - 1; - } - /* Select which calling sequence. */ info->abi = DEFAULT_ABI; @@ -27219,21 +26264,6 @@ rs6000_stack_info (void) info->gp_size = reg_size * (32 - first_gp); - /* For the SPE, we have an additional upper 32-bits on each GPR. - Ideally we should save the entire 64-bits only when the upper - half is used in SIMD instructions. Since we only record - registers live (not the size they are used in), this proves - difficult because we'd have to traverse the instruction chain at - the right time, taking reload into account. This is a real pain, - so we opt to save the GPRs in 64-bits always if but one register - gets used in 64-bits. Otherwise, all the registers in the frame - get saved in 32-bits. - - So... since when we save all GPRs (except the SP) in 64-bits, the - traditional GP save area will be empty. */ - if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) - info->gp_size = 0; - info->first_fp_reg_save = first_fp_reg_to_save (); info->fp_size = 8 * (64 - info->first_fp_reg_save); @@ -27263,9 +26293,7 @@ rs6000_stack_info (void) for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) continue; - /* SPE saves EH registers in 64-bits. */ - ehrd_size = i * (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0 - ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); + ehrd_size = i * UNITS_PER_WORD; } else ehrd_size = 0; @@ -27299,9 +26327,6 @@ rs6000_stack_info (void) ABI_STACK_BOUNDARY / BITS_PER_UNIT) - (info->fixed_size + info->vars_size + info->parm_size); - if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) - info->spe_gp_size = 8 * (32 - first_gp); - if (TARGET_ALTIVEC_ABI) info->vrsave_mask = compute_vrsave_mask (); @@ -27354,23 +26379,7 @@ rs6000_stack_info (void) info->gp_save_offset = info->fp_save_offset - info->gp_size; info->cr_save_offset = info->gp_save_offset - info->cr_size; - if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) - { - /* Align stack so SPE GPR save area is aligned on a - double-word boundary. */ - if (info->spe_gp_size != 0 && info->cr_save_offset != 0) - info->spe_padding_size = 8 - (-info->cr_save_offset % 8); - else - info->spe_padding_size = 0; - - info->spe_gp_save_offset = info->cr_save_offset - - info->spe_padding_size - - info->spe_gp_size; - - /* Adjust for SPE case. */ - info->ehrd_offset = info->spe_gp_save_offset; - } - else if (TARGET_ALTIVEC_ABI) + if (TARGET_ALTIVEC_ABI) { info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size; @@ -27397,8 +26406,6 @@ rs6000_stack_info (void) + info->gp_size + info->altivec_size + info->altivec_padding_size - + info->spe_gp_size - + info->spe_padding_size + ehrd_size + ehcr_size + info->cr_size @@ -27470,50 +26477,6 @@ rs6000_stack_info (void) return info; } -/* Return true if the current function uses any GPRs in 64-bit SIMD - mode. */ - -static bool -spe_func_has_64bit_regs_p (void) -{ - rtx_insn *insns, *insn; - - /* Functions that save and restore all the call-saved registers will - need to save/restore the registers in 64-bits. */ - if (crtl->calls_eh_return - || cfun->calls_setjmp - || crtl->has_nonlocal_goto) - return true; - - insns = get_insns (); - - for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn)) - { - if (INSN_P (insn)) - { - rtx i; - - /* FIXME: This should be implemented with attributes... - - (set_attr "spe64" "true")....then, - if (get_spe64(insn)) return true; - - It's the only reliable way to do the stuff below. */ - - i = PATTERN (insn); - if (GET_CODE (i) == SET) - { - machine_mode mode = GET_MODE (SET_SRC (i)); - - if (SPE_VECTOR_MODE (mode)) - return true; - } - } - } - - return false; -} - static void debug_stack_info (rs6000_stack_t *info) { @@ -27542,9 +26505,6 @@ debug_stack_info (rs6000_stack_t *info) if (TARGET_ALTIVEC_ABI) fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); - if (TARGET_SPE_ABI) - fprintf (stderr, "\tSPE ABI extensions enabled.\n"); - if (info->first_gp_reg_save != 32) fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); @@ -27580,10 +26540,6 @@ debug_stack_info (rs6000_stack_t *info) fprintf (stderr, "\taltivec_save_offset = %5d\n", info->altivec_save_offset); - if (info->spe_gp_size) - fprintf (stderr, "\tspe_gp_save_offset = %5d\n", - info->spe_gp_save_offset); - if (info->vrsave_size) fprintf (stderr, "\tvrsave_save_offset = %5d\n", info->vrsave_save_offset); @@ -27614,9 +26570,6 @@ debug_stack_info (rs6000_stack_t *info) if (info->gp_size) fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); - if (info->spe_gp_size) - fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); - if (info->fp_size) fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); @@ -27630,10 +26583,6 @@ debug_stack_info (rs6000_stack_t *info) fprintf (stderr, "\taltivec_padding_size= %5d\n", info->altivec_padding_size); - if (info->spe_padding_size) - fprintf (stderr, "\tspe_padding_size = %5d\n", - info->spe_padding_size); - if (info->cr_size) fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); @@ -28453,11 +27402,8 @@ emit_frame_save (rtx frame_reg, machine_mode mode, rtx reg; /* Some cases that need register indexed addressing. */ - gcc_checking_assert (!((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) - || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)) - || (TARGET_SPE_ABI - && SPE_VECTOR_MODE (mode) - && !SPE_CONST_OFFSET_OK (offset)))); + gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) + || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode))); reg = gen_rtx_REG (mode, regno); rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset)); @@ -28471,19 +27417,7 @@ emit_frame_save (rtx frame_reg, machine_mode mode, static rtx gen_frame_mem_offset (machine_mode mode, rtx reg, int offset) { - rtx int_rtx, offset_rtx; - - int_rtx = GEN_INT (offset); - - if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode) && !SPE_CONST_OFFSET_OK (offset)) - { - offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); - emit_move_insn (offset_rtx, int_rtx); - } - else - offset_rtx = int_rtx; - - return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); + return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset))); } #ifndef TARGET_FIX_AND_CONTINUE @@ -28514,7 +27448,7 @@ static char savres_routine_name[30]; We are saving/restoring GPRs if GPR is true. */ static char * -rs6000_savres_routine_name (rs6000_stack_t *info, int regno, int sel) +rs6000_savres_routine_name (int regno, int sel) { const char *prefix = ""; const char *suffix = ""; @@ -28530,9 +27464,6 @@ rs6000_savres_routine_name (rs6000_stack_t *info, int regno, int sel) - ELF targets have save/restore routines for GPRs. - - SPE targets use different prefixes for 32/64-bit registers, and - neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen. - - PPC64 ELF targets have routines for save/restore of GPRs that differ in what they do with the link register, so having a set prefix doesn't work. (We only use one of the save routines at @@ -28547,20 +27478,7 @@ rs6000_savres_routine_name (rs6000_stack_t *info, int regno, int sel) We deal with all this by synthesizing our own prefix/suffix and using that for the simple sprintf call shown above. */ - if (TARGET_SPE) - { - /* No floating point saves on the SPE. */ - gcc_assert ((sel & SAVRES_REG) == SAVRES_GPR); - - if ((sel & SAVRES_SAVE)) - prefix = info->spe_64bit_regs_used ? "_save64gpr_" : "_save32gpr_"; - else - prefix = info->spe_64bit_regs_used ? "_rest64gpr_" : "_rest32gpr_"; - - if ((sel & SAVRES_LR)) - suffix = "_x"; - } - else if (DEFAULT_ABI == ABI_V4) + if (DEFAULT_ABI == ABI_V4) { if (TARGET_64BIT) goto aix_names; @@ -28650,12 +27568,6 @@ rs6000_savres_routine_sym (rs6000_stack_t *info, int sel) rtx sym; int select = sel; - /* On the SPE, we never have any FPRs, but we do have 32/64-bit - versions of the gpr routines. */ - if (TARGET_SPE_ABI && (sel & SAVRES_REG) == SAVRES_GPR - && info->spe_64bit_regs_used) - select ^= SAVRES_FPR ^ SAVRES_GPR; - /* Don't generate bogus routine names. */ gcc_assert (FIRST_SAVRES_REGISTER <= regno && regno <= LAST_SAVRES_REGISTER @@ -28667,7 +27579,7 @@ rs6000_savres_routine_sym (rs6000_stack_t *info, int sel) { char *name; - name = rs6000_savres_routine_name (info, regno, sel); + name = rs6000_savres_routine_name (regno, sel); sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); @@ -28683,8 +27595,7 @@ rs6000_savres_routine_sym (rs6000_stack_t *info, int sel) reg UPDT_REGNO for use by out-of-line register restore routines. */ static rtx -rs6000_emit_stack_reset (rs6000_stack_t *info, - rtx frame_reg_rtx, HOST_WIDE_INT frame_off, +rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off, unsigned updt_regno) { /* If there is nothing to do, don't do anything. */ @@ -28695,10 +27606,7 @@ rs6000_emit_stack_reset (rs6000_stack_t *info, /* This blockage is needed so that sched doesn't decide to move the sp change before the register restores. */ - if (DEFAULT_ABI == ABI_V4 - || (TARGET_SPE_ABI - && info->spe_64bit_regs_used != 0 - && info->first_gp_reg_save != 32)) + if (DEFAULT_ABI == ABI_V4) return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx, GEN_INT (frame_off))); @@ -28920,9 +27828,6 @@ rs6000_get_separate_components (void) if (WORLD_SAVE_P (info)) return NULL; - if (TARGET_SPE_ABI) - return NULL; - gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE) && !(info->savres_strategy & REST_MULTIPLE)); @@ -29318,12 +28223,6 @@ rs6000_emit_prologue (void) emit_insn (gen_nop ()); } - if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) - { - reg_mode = V2SImode; - reg_size = 8; - } - /* Handle world saves specially here. */ if (WORLD_SAVE_P (info)) { @@ -29424,12 +28323,9 @@ rs6000_emit_prologue (void) && (DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return)) { - bool need_r11 = (TARGET_SPE - ? (!(strategy & SAVE_INLINE_GPRS) - && info->spe_64bit_regs_used == 0) - : (!(strategy & SAVE_INLINE_FPRS) - || !(strategy & SAVE_INLINE_GPRS) - || !(strategy & SAVE_INLINE_VRS))); + bool need_r11 = (!(strategy & SAVE_INLINE_FPRS) + || !(strategy & SAVE_INLINE_GPRS) + || !(strategy & SAVE_INLINE_VRS)); int ptr_regno = -1; rtx ptr_reg = NULL_RTX; int ptr_off = 0; @@ -29566,94 +28462,7 @@ rs6000_emit_prologue (void) /* Save GPRs. This is done as a PARALLEL if we are using the store-multiple instructions. */ - if (!WORLD_SAVE_P (info) - && TARGET_SPE_ABI - && info->spe_64bit_regs_used != 0 - && info->first_gp_reg_save != 32) - { - int i; - rtx spe_save_area_ptr; - HOST_WIDE_INT save_off; - int ool_adjust = 0; - - /* Determine whether we can address all of the registers that need - to be saved with an offset from frame_reg_rtx that fits in - the small const field for SPE memory instructions. */ - int spe_regs_addressable - = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + frame_off - + reg_size * (32 - info->first_gp_reg_save - 1)) - && (strategy & SAVE_INLINE_GPRS)); - - if (spe_regs_addressable) - { - spe_save_area_ptr = frame_reg_rtx; - save_off = frame_off; - } - else - { - /* Make r11 point to the start of the SPE save area. We need - to be careful here if r11 is holding the static chain. If - it is, then temporarily save it in r0. */ - HOST_WIDE_INT offset; - - if (!(strategy & SAVE_INLINE_GPRS)) - ool_adjust = 8 * (info->first_gp_reg_save - FIRST_SAVED_GP_REGNO); - offset = info->spe_gp_save_offset + frame_off - ool_adjust; - spe_save_area_ptr = gen_rtx_REG (Pmode, 11); - save_off = frame_off - offset; - - if (using_static_chain_p) - { - rtx r0 = gen_rtx_REG (Pmode, 0); - - START_USE (0); - gcc_assert (info->first_gp_reg_save > 11); - - emit_move_insn (r0, spe_save_area_ptr); - } - else if (REGNO (frame_reg_rtx) != 11) - START_USE (11); - - emit_insn (gen_addsi3 (spe_save_area_ptr, - frame_reg_rtx, GEN_INT (offset))); - if (!using_static_chain_p && REGNO (frame_reg_rtx) == 11) - frame_off = -info->spe_gp_save_offset + ool_adjust; - } - - if ((strategy & SAVE_INLINE_GPRS)) - { - for (i = 0; i < 32 - info->first_gp_reg_save; i++) - if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i)) - emit_frame_save (spe_save_area_ptr, reg_mode, - info->first_gp_reg_save + i, - (info->spe_gp_save_offset + save_off - + reg_size * i), - sp_off - save_off); - } - else - { - insn = rs6000_emit_savres_rtx (info, spe_save_area_ptr, - info->spe_gp_save_offset + save_off, - 0, reg_mode, - SAVRES_SAVE | SAVRES_GPR); - - rs6000_frame_related (insn, spe_save_area_ptr, sp_off - save_off, - NULL_RTX, NULL_RTX); - } - - /* Move the static chain pointer back. */ - if (!spe_regs_addressable) - { - if (using_static_chain_p) - { - emit_move_insn (spe_save_area_ptr, gen_rtx_REG (Pmode, 0)); - END_USE (0); - } - else if (REGNO (frame_reg_rtx) != 11) - END_USE (11); - } - } - else if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS)) + if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS)) { bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0; int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0); @@ -30280,7 +29089,7 @@ rs6000_output_savres_externs (FILE *file) { bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0; int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0); - name = rs6000_savres_routine_name (info, regno, sel); + name = rs6000_savres_routine_name (regno, sel); fprintf (file, "\t.extern %s\n", name); } if ((info->savres_strategy & REST_INLINE_FPRS) == 0) @@ -30288,7 +29097,7 @@ rs6000_output_savres_externs (FILE *file) bool lr = (info->savres_strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0; int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0); - name = rs6000_savres_routine_name (info, regno, sel); + name = rs6000_savres_routine_name (regno, sel); fprintf (file, "\t.extern %s\n", name); } } @@ -30619,12 +29428,6 @@ rs6000_emit_epilogue (int sibcall) info = rs6000_stack_info (); - if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) - { - reg_mode = V2SImode; - reg_size = 8; - } - strategy = info->savres_strategy; using_load_multiple = strategy & REST_MULTIPLE; restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS); @@ -31179,68 +29982,7 @@ rs6000_emit_epilogue (int sibcall) /* Restore GPRs. This is done as a PARALLEL if we are using the load-multiple instructions. */ - if (TARGET_SPE_ABI - && info->spe_64bit_regs_used - && info->first_gp_reg_save != 32) - { - /* Determine whether we can address all of the registers that need - to be saved with an offset from frame_reg_rtx that fits in - the small const field for SPE memory instructions. */ - int spe_regs_addressable - = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + frame_off - + reg_size * (32 - info->first_gp_reg_save - 1)) - && restoring_GPRs_inline); - - if (!spe_regs_addressable) - { - int ool_adjust = 0; - rtx old_frame_reg_rtx = frame_reg_rtx; - /* Make r11 point to the start of the SPE save area. We worried about - not clobbering it when we were saving registers in the prologue. - There's no need to worry here because the static chain is passed - anew to every function. */ - - if (!restoring_GPRs_inline) - ool_adjust = 8 * (info->first_gp_reg_save - FIRST_SAVED_GP_REGNO); - frame_reg_rtx = gen_rtx_REG (Pmode, 11); - emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx, - GEN_INT (info->spe_gp_save_offset - + frame_off - - ool_adjust))); - /* Keep the invariant that frame_reg_rtx + frame_off points - at the top of the stack frame. */ - frame_off = -info->spe_gp_save_offset + ool_adjust; - } - - if (restoring_GPRs_inline) - { - HOST_WIDE_INT spe_offset = info->spe_gp_save_offset + frame_off; - - for (i = 0; i < 32 - info->first_gp_reg_save; i++) - if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i)) - { - rtx offset, addr, mem, reg; - - /* We're doing all this to ensure that the immediate offset - fits into the immediate field of 'evldd'. */ - gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i)); - - offset = GEN_INT (spe_offset + reg_size * i); - addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset); - mem = gen_rtx_MEM (V2SImode, addr); - reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); - - emit_move_insn (reg, mem); - } - } - else - rs6000_emit_savres_rtx (info, frame_reg_rtx, - info->spe_gp_save_offset + frame_off, - info->lr_save_offset + frame_off, - reg_mode, - SAVRES_GPR | SAVRES_LR); - } - else if (!restoring_GPRs_inline) + if (!restoring_GPRs_inline) { /* We are jumping to an out-of-line function. */ rtx ptr_reg; @@ -31253,7 +29995,7 @@ rs6000_emit_epilogue (int sibcall) ptr_regno = ptr_regno_for_savres (sel); ptr_reg = gen_rtx_REG (Pmode, ptr_regno); if (can_use_exit) - rs6000_emit_stack_reset (info, frame_reg_rtx, frame_off, ptr_regno); + rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno); else if (end_save + frame_off != 0) emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, GEN_INT (end_save + frame_off))); @@ -31391,7 +30133,7 @@ rs6000_emit_epilogue (int sibcall) ptr_regno = ptr_regno_for_savres (sel); } - insn = rs6000_emit_stack_reset (info, frame_reg_rtx, frame_off, ptr_regno); + insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno); if (REGNO (frame_reg_rtx) == ptr_regno) frame_off = 0; @@ -36252,9 +34994,7 @@ rs6000_elf_file_end (void) { if (rs6000_passes_vector) fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n", - (TARGET_ALTIVEC_ABI ? 2 - : TARGET_SPE_ABI ? 3 - : 1)); + (TARGET_ALTIVEC_ABI ? 2 : 1)); if (rs6000_returns_struct) fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n", aix_struct_return ? 2 : 1); @@ -38343,8 +37083,7 @@ rs6000_vectorize_vec_perm_const_ok (machine_mode vmode, return true; /* Check for ps_merge* or evmerge* insns. */ - if ((TARGET_PAIRED_FLOAT && vmode == V2SFmode) - || (TARGET_SPE && vmode == V2SImode)) + if (TARGET_PAIRED_FLOAT && vmode == V2SFmode) { rtx op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1); rtx op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2); @@ -38704,68 +37443,11 @@ rs6000_initial_elimination_offset (int from, int to) return offset; } -static rtx -rs6000_dwarf_register_span (rtx reg) -{ - rtx parts[8]; - int i, words; - unsigned regno = REGNO (reg); - machine_mode mode = GET_MODE (reg); - - if (TARGET_SPE - && regno < 32 - && SPE_VECTOR_MODE (GET_MODE (reg))) - ; - else - return NULL_RTX; - - regno = REGNO (reg); - - /* The duality of the SPE register size wreaks all kinds of havoc. - This is a way of distinguishing r0 in 32-bits from r0 in - 64-bits. */ - words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; - gcc_assert (words <= 4); - for (i = 0; i < words; i++, regno++) - { - if (BYTES_BIG_ENDIAN) - { - parts[2 * i] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO); - parts[2 * i + 1] = gen_rtx_REG (SImode, regno); - } - else - { - parts[2 * i] = gen_rtx_REG (SImode, regno); - parts[2 * i + 1] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO); - } - } - - return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts)); -} - /* Fill in sizes for SPE register high parts in table used by unwinder. */ static void rs6000_init_dwarf_reg_sizes_extra (tree address) { - if (TARGET_SPE) - { - int i; - machine_mode mode = TYPE_MODE (char_type_node); - rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL); - rtx mem = gen_rtx_MEM (BLKmode, addr); - rtx value = gen_int_mode (4, mode); - - for (i = FIRST_SPE_HIGH_REGNO; i < LAST_SPE_HIGH_REGNO+1; i++) - { - int column = DWARF_REG_TO_UNWIND_COLUMN - (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true)); - HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode); - - emit_move_insn (adjust_address (mem, mode, offset), value); - } - } - if (TARGET_MACHO && ! TARGET_ALTIVEC) { int i; @@ -38797,11 +37479,6 @@ rs6000_init_dwarf_reg_sizes_extra (tree address) unsigned int rs6000_dbx_register_number (unsigned int regno, unsigned int format) { - /* We never use the GCC internal number for SPE high registers. - Those are mapped to the 1200..1231 range for all debug formats. */ - if (SPE_HIGH_REGNO_P (regno)) - return regno - FIRST_SPE_HIGH_REGNO + 1200; - /* Except for the above, we use the internal number for non-DWARF debug information, and also for .eh_frame. */ if ((format == 0 && write_symbols != DWARF2_DEBUG) || format == 2) @@ -38875,9 +37552,6 @@ rs6000_vector_mode_supported_p (machine_mode mode) if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode)) return true; - if (TARGET_SPE && SPE_VECTOR_MODE (mode)) - return true; - /* There is no vector form for IEEE 128-bit. If we return true for IEEE 128-bit, the compiler might try to widen IEEE 128-bit to IBM double-double. */ @@ -39083,7 +37757,6 @@ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] = { { "altivec", RS6000_BTM_ALTIVEC, false, false }, { "vsx", RS6000_BTM_VSX, false, false }, - { "spe", RS6000_BTM_SPE, false, false }, { "paired", RS6000_BTM_PAIRED, false, false }, { "fre", RS6000_BTM_FRE, false, false }, { "fres", RS6000_BTM_FRES, false, false }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 66f8170d68a..da3b8777a54 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -569,8 +569,6 @@ extern int rs6000_vector_align[]; #define TARGET_ALTIVEC_ABI rs6000_altivec_abi #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) -#define TARGET_SPE_ABI 0 -#define TARGET_SPE 0 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64) /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. @@ -704,7 +702,7 @@ extern int rs6000_vector_align[]; the compiler for those builtins, and those machines don't support altivec or VSX. */ -#define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \ +#define TARGET_EXTRA_BUILTINS (!TARGET_PAIRED_FLOAT \ && ((TARGET_POWERPC64 \ || TARGET_PPC_GPOPT /* 970/power4 */ \ || TARGET_POPCNTB /* ISA 2.02 */ \ @@ -869,7 +867,6 @@ extern unsigned char rs6000_recip_bits[]; #define UNITS_PER_FP_WORD 8 #define UNITS_PER_ALTIVEC_WORD 16 #define UNITS_PER_VSX_WORD 16 -#define UNITS_PER_SPE_WORD 8 #define UNITS_PER_PAIRED_WORD 8 /* Type used for ptrdiff_t, as a string used in a declaration. */ @@ -971,8 +968,7 @@ enum data_align { align_abi, align_opt, align_both }; #define DATA_ALIGNMENT(TYPE, ALIGN) \ rs6000_data_alignment (TYPE, ALIGN, align_opt) -/* Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to - 64 bits. */ +/* Align vectors to 128 bits. */ #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ rs6000_data_alignment (TYPE, ALIGN, align_abi) @@ -983,9 +979,8 @@ enum data_align { align_abi, align_opt, align_both }; /* Define this macro to be the value 1 if unaligned accesses have a cost many times greater than aligned accesses, for example if they are emulated in a trap handler. */ -/* Altivec vector memory instructions simply ignore the low bits; SPE vector - memory instructions trap on unaligned accesses; VSX memory instructions are - aligned to 4 or 8 bytes. */ +/* Altivec vector memory instructions simply ignore the low bits; VSX memory + instructions are aligned to 4 or 8 bytes. */ #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ (STRICT_ALIGNMENT \ || (!TARGET_EFFICIENT_UNALIGNED_VSX \ @@ -1027,12 +1022,7 @@ enum data_align { align_abi, align_opt, align_both }; /* This must be included for pre gcc 3.0 glibc compatibility. */ #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 -/* True if register is an SPE High register. */ -#define SPE_HIGH_REGNO_P(N) \ - ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO) - -/* SPE high registers added as hard regs. - The sfp register and 3 HTM registers +/* The sfp register and 3 HTM registers aren't included in DWARF_FRAME_REGISTERS. */ #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) @@ -1227,9 +1217,6 @@ enum data_align { align_abi, align_opt, align_both }; #define INT_REGNO_P(N) \ ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) -/* SPE SIMD registers are just the GPRs. */ -#define SPE_SIMD_REGNO_P(N) ((N) <= 31) - /* PAIRED SIMD registers are just the FPRs. */ #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) @@ -1305,12 +1292,6 @@ enum data_align { align_abi, align_opt, align_both }; (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ || (MODE) == V2DImode || (MODE) == V1TImode) -#define SPE_VECTOR_MODE(MODE) \ - ((MODE) == V4HImode \ - || (MODE) == V2SFmode \ - || (MODE) == V1DImode \ - || (MODE) == V2SImode) - #define PAIRED_VECTOR_MODE(MODE) \ ((MODE) == V2SFmode) @@ -1347,9 +1328,9 @@ enum data_align { align_abi, align_opt, align_both }; ? GET_MODE_CLASS (MODE2) == MODE_CC \ : GET_MODE_CLASS (MODE2) == MODE_CC \ ? 0 \ - : SPE_VECTOR_MODE (MODE1) \ - ? SPE_VECTOR_MODE (MODE2) \ - : SPE_VECTOR_MODE (MODE2) \ + : PAIRED_VECTOR_MODE (MODE1) \ + ? PAIRED_VECTOR_MODE (MODE2) \ + : PAIRED_VECTOR_MODE (MODE2) \ ? 0 \ : 1) @@ -2684,7 +2665,7 @@ extern int frame_pointer_needed; #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ /* Builtin targets. For now, we reuse the masks for those options that are in - target flags, and pick three random bits for SPE, paired and ldbl128 which + target flags, and pick two random bits for paired and ldbl128, which aren't in target_flags. */ #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ @@ -2695,7 +2676,6 @@ extern int frame_pointer_needed; #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ -#define RS6000_BTM_SPE MASK_STRING /* E500 */ #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ @@ -2736,11 +2716,9 @@ extern int frame_pointer_needed; #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, @@ -2749,11 +2727,9 @@ extern int frame_pointer_needed; #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, enum rs6000_builtins @@ -2769,11 +2745,9 @@ enum rs6000_builtins #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_E #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q -#undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X enum rs6000_builtin_type_index diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 997d1fe9292..3fea231665d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -56,8 +56,6 @@ (TFHAR_REGNO 114) (TFIAR_REGNO 115) (TEXASR_REGNO 116) - (FIRST_SPE_HIGH_REGNO 117) - (LAST_SPE_HIGH_REGNO 148) ]) ;; diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index c5c11c53593..a1a775389da 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -381,14 +381,6 @@ mabi=no-altivec Target RejectNegative Var(rs6000_altivec_abi, 0) Do not use the AltiVec ABI extensions. -mabi=spe -Target RejectNegative Var(rs6000_spe_abi) Save -Use the SPE ABI extensions. - -mabi=no-spe -Target RejectNegative Var(rs6000_spe_abi, 0) -Do not use the SPE ABI extensions. - mabi=elfv1 Target RejectNegative Var(rs6000_elf_abi, 1) Save Use the ELFv1 ABI. diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index 536697b8a9c..372e1901759 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -26,2770 +26,3 @@ ;; DImode and TImode. (define_mode_iterator DITI [DI TI]) - -;; SPE SIMD instructions - -(define_insn "absv2si2" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] - "TARGET_SPE" - "evabs %0,%1" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evandc" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") - (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] - "TARGET_SPE" - "evandc %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "andv2si3" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")))] - "TARGET_SPE" - "evand %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -;; Vector compare instructions - -(define_insn "spe_evcmpeq" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))] - "TARGET_SPE" - "evcmpeq %0,%1,%2" - [(set_attr "type" "veccmp") - (set_attr "length" "4")]) - -(define_insn "spe_evcmpgts" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))] - "TARGET_SPE" - "evcmpgts %0,%1,%2" - [(set_attr "type" "veccmp") - (set_attr "length" "4")]) - -(define_insn "spe_evcmpgtu" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))] - "TARGET_SPE" - "evcmpgtu %0,%1,%2" - [(set_attr "type" "veccmp") - (set_attr "length" "4")]) - -(define_insn "spe_evcmplts" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))] - "TARGET_SPE" - "evcmplts %0,%1,%2" - [(set_attr "type" "veccmp") - (set_attr "length" "4")]) - -(define_insn "spe_evcmpltu" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))] - "TARGET_SPE" - "evcmpltu %0,%1,%2" - [(set_attr "type" "veccmp") - (set_attr "length" "4")]) - -;; Floating point vector compare instructions - -(define_insn "spe_evfscmpeq" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") - (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538)) - (clobber (reg:SI SPEFSCR_REGNO))] - "TARGET_SPE" - "evfscmpeq %0,%1,%2" - [(set_attr "type" "veccmp") - (set_attr "length" "4")]) - -(define_insn "spe_evfscmpgt" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") - (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539)) - (clobber (reg:SI SPEFSCR_REGNO))] - "TARGET_SPE" - "evfscmpgt %0,%1,%2" - [(set_attr "type" "veccmp") - (set_attr "length" "4")]) - -(define_insn "spe_evfscmplt" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") - (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540)) - (clobber (reg:SI SPEFSCR_REGNO))] - "TARGET_SPE" - "evfscmplt %0,%1,%2" - [(set_attr "type" "veccmp") - (set_attr "length" "4")]) - -(define_insn "spe_evfststeq" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") - (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))] - "TARGET_SPE" - "evfststeq %0,%1,%2" - [(set_attr "type" "veccmp") - (set_attr "length" "4")]) - -(define_insn "spe_evfststgt" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") - (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))] - "TARGET_SPE" - "evfststgt %0,%1,%2" - [(set_attr "type" "veccmp") - (set_attr "length" "4")]) - -(define_insn "spe_evfststlt" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") - (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))] - "TARGET_SPE" - "evfststlt %0,%1,%2" - [(set_attr "type" "veccmp") - (set_attr "length" "4")]) - -;; End of vector compare instructions - -(define_insn "spe_evcntlsw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))] - "TARGET_SPE" - "evcntlsw %0,%1" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evcntlzw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))] - "TARGET_SPE" - "evcntlzw %0,%1" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_eveqv" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] - "TARGET_SPE" - "eveqv %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evextsb" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))] - "TARGET_SPE" - "evextsb %0,%1" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evextsh" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))] - "TARGET_SPE" - "evextsh %0,%1" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evlhhesplat" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:QI 2 "immediate_operand" "i")))) - (unspec [(const_int 0)] 509)] - "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" - "evlhhesplat %0,%2*2(%1)" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlhhesplatx" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:SI 2 "gpc_reg_operand" "r")))) - (unspec [(const_int 0)] 510)] - "TARGET_SPE" - "evlhhesplatx %0,%1,%2" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlhhossplat" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:QI 2 "immediate_operand" "i")))) - (unspec [(const_int 0)] 511)] - "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" - "evlhhossplat %0,%2*2(%1)" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlhhossplatx" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:SI 2 "gpc_reg_operand" "r")))) - (unspec [(const_int 0)] 512)] - "TARGET_SPE" - "evlhhossplatx %0,%1,%2" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlhhousplat" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:QI 2 "immediate_operand" "i")))) - (unspec [(const_int 0)] 513)] - "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" - "evlhhousplat %0,%2*2(%1)" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlhhousplatx" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:SI 2 "gpc_reg_operand" "r")))) - (unspec [(const_int 0)] 514)] - "TARGET_SPE" - "evlhhousplatx %0,%1,%2" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlwhsplat" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:QI 2 "immediate_operand" "i")))) - (unspec [(const_int 0)] 515)] - "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" - "evlwhsplat %0,%2*4(%1)" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlwhsplatx" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:SI 2 "gpc_reg_operand" "r")))) - (unspec [(const_int 0)] 516)] - "TARGET_SPE" - "evlwhsplatx %0,%1,%2" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlwwsplat" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:QI 2 "immediate_operand" "i")))) - (unspec [(const_int 0)] 517)] - "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" - "evlwwsplat %0,%2*4(%1)" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlwwsplatx" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:SI 2 "gpc_reg_operand" "r")))) - (unspec [(const_int 0)] 518)] - "TARGET_SPE" - "evlwwsplatx %0,%1,%2" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -;; Integer vector permutation instructions. The pairs of digits in the -;; names of these instructions indicate the indices, in the memory vector -;; element ordering, of the vector elements permuted to the output vector -;; from the first and the second input vector respectively. - -(define_insn "vec_perm00_v2si" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (vec_select:V2SI - (vec_concat:V4SI - (match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (parallel [(const_int 0) (const_int 2)])))] - "TARGET_SPE" -{ - if (WORDS_BIG_ENDIAN) - return "evmergehi %0,%1,%2"; - else - return "evmergelo %0,%2,%1"; -} - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "vec_perm01_v2si" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (vec_select:V2SI - (vec_concat:V4SI - (match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (parallel [(const_int 0) (const_int 3)])))] - "TARGET_SPE" -{ - if (WORDS_BIG_ENDIAN) - return "evmergehilo %0,%1,%2"; - else - return "evmergehilo %0,%2,%1"; -} - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "vec_perm11_v2si" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (vec_select:V2SI - (vec_concat:V4SI - (match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (parallel [(const_int 1) (const_int 3)])))] - "TARGET_SPE" -{ - if (WORDS_BIG_ENDIAN) - return "evmergelo %0,%1,%2"; - else - return "evmergehi %0,%2,%1"; -} - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "vec_perm10_v2si" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (vec_select:V2SI - (vec_concat:V4SI - (match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (parallel [(const_int 1) (const_int 2)])))] - "TARGET_SPE" -{ - if (WORDS_BIG_ENDIAN) - return "evmergelohi %0,%1,%2"; - else - return "evmergelohi %0,%2,%1"; -} - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_expand "vec_perm_constv2si" - [(match_operand:V2SI 0 "gpc_reg_operand" "") - (match_operand:V2SI 1 "gpc_reg_operand" "") - (match_operand:V2SI 2 "gpc_reg_operand" "") - (match_operand:V2SI 3 "" "")] - "TARGET_SPE" -{ - if (rs6000_expand_vec_perm_const (operands)) - DONE; - else - FAIL; -}) - -(define_expand "spe_evmergehi" - [(match_operand:V2SI 0 "register_operand" "") - (match_operand:V2SI 1 "register_operand" "") - (match_operand:V2SI 2 "register_operand" "")] - "TARGET_SPE" -{ - if (BYTES_BIG_ENDIAN) - emit_insn (gen_vec_perm00_v2si (operands[0], operands[1], operands[2])); - else - emit_insn (gen_vec_perm11_v2si (operands[0], operands[2], operands[1])); - DONE; -}) - -(define_expand "spe_evmergehilo" - [(match_operand:V2SI 0 "register_operand" "") - (match_operand:V2SI 1 "register_operand" "") - (match_operand:V2SI 2 "register_operand" "")] - "TARGET_SPE" -{ - if (BYTES_BIG_ENDIAN) - emit_insn (gen_vec_perm01_v2si (operands[0], operands[1], operands[2])); - else - emit_insn (gen_vec_perm01_v2si (operands[0], operands[2], operands[1])); - DONE; -}) - -(define_expand "spe_evmergelo" - [(match_operand:V2SI 0 "register_operand" "") - (match_operand:V2SI 1 "register_operand" "") - (match_operand:V2SI 2 "register_operand" "")] - "TARGET_SPE" -{ - if (BYTES_BIG_ENDIAN) - emit_insn (gen_vec_perm11_v2si (operands[0], operands[1], operands[2])); - else - emit_insn (gen_vec_perm00_v2si (operands[0], operands[2], operands[1])); - DONE; -}) - -(define_expand "spe_evmergelohi" - [(match_operand:V2SI 0 "register_operand" "") - (match_operand:V2SI 1 "register_operand" "") - (match_operand:V2SI 2 "register_operand" "")] - "TARGET_SPE" -{ - if (BYTES_BIG_ENDIAN) - emit_insn (gen_vec_perm10_v2si (operands[0], operands[1], operands[2])); - else - emit_insn (gen_vec_perm10_v2si (operands[0], operands[2], operands[1])); - DONE; -}) - -;; End of integer vector permutation instructions. - -(define_insn "spe_evnand" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] - "TARGET_SPE" - "evnand %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "negv2si2" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] - "TARGET_SPE" - "evneg %0,%1" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evnor" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] - "TARGET_SPE" - "evnor %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evorc" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") - (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] - "TARGET_SPE" - "evorc %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evor" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")))] - "TARGET_SPE" - "evor %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evrlwi" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:QI 2 "immediate_operand" "i")] 519))] - "TARGET_SPE" - "evrlwi %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evrlw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))] - "TARGET_SPE" - "evrlw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evrndw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))] - "TARGET_SPE" - "evrndw %0,%1" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evsel" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (match_operand:CC 3 "cc_reg_operand" "y")] 522))] - "TARGET_SPE" - "evsel %0,%1,%2,%3" - [(set_attr "type" "veccmp") - (set_attr "length" "4")]) - -(define_insn "spe_evsel_fs" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") - (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r") - (match_operand:V2SF 2 "gpc_reg_operand" "r") - (match_operand:CC 3 "cc_reg_operand" "y")] 725))] - "TARGET_SPE" - "evsel %0,%1,%2,%3" - [(set_attr "type" "veccmp") - (set_attr "length" "4")]) - -(define_insn "spe_evslwi" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:QI 2 "immediate_operand" "i")] - 523))] - "TARGET_SPE" - "evslwi %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evslw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))] - "TARGET_SPE" - "evslw %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evsrwis" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:QI 2 "immediate_operand" "i")] - 525))] - "TARGET_SPE" - "evsrwis %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evsrwiu" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:QI 2 "immediate_operand" "i")] - 526))] - "TARGET_SPE" - "evsrwiu %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evsrws" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))] - "TARGET_SPE" - "evsrws %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evsrwu" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))] - "TARGET_SPE" - "evsrwu %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -;; vector xors - -(define_insn "xorv2si3" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")))] - "TARGET_SPE" - "evxor %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "xorv4hi3" - [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r") - (xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r") - (match_operand:V4HI 2 "gpc_reg_operand" "r")))] - "TARGET_SPE" - "evxor %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "xorv1di3" - [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r") - (xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r") - (match_operand:V1DI 2 "gpc_reg_operand" "r")))] - "TARGET_SPE" - "evxor %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -;; end of vector xors - -(define_insn "spe_evfsabs" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") - (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))] - "TARGET_SPE" - "evfsabs %0,%1" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evfsadd" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") - (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") - (match_operand:V2SF 2 "gpc_reg_operand" "r"))) - (clobber (reg:SI SPEFSCR_REGNO))] - "TARGET_SPE" - "evfsadd %0,%1,%2" - [(set_attr "type" "vecfloat") - (set_attr "length" "4")]) - -(define_insn "spe_evfscfsf" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") - (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))] - "TARGET_SPE" - "evfscfsf %0,%1" - [(set_attr "type" "vecfloat") - (set_attr "length" "4")]) - -(define_insn "spe_evfscfsi" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") - (float:V2SF (match_operand:V2SI 1 "gpc_reg_operand" "r")))] - "TARGET_SPE" - "evfscfsi %0,%1" - [(set_attr "type" "vecfloat") - (set_attr "length" "4")]) - -(define_insn "spe_evfscfuf" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") - (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))] - "TARGET_SPE" - "evfscfuf %0,%1" - [(set_attr "type" "vecfloat") - (set_attr "length" "4")]) - -(define_insn "spe_evfscfui" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") - (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))] - "TARGET_SPE" - "evfscfui %0,%1" - [(set_attr "type" "vecfloat") - (set_attr "length" "4")]) - -(define_insn "spe_evfsctsf" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") - (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))] - "TARGET_SPE" - "evfsctsf %0,%1" - [(set_attr "type" "vecfloat") - (set_attr "length" "4")]) - -(define_insn "spe_evfsctsi" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))] - "TARGET_SPE" - "evfsctsi %0,%1" - [(set_attr "type" "vecfloat") - (set_attr "length" "4")]) - -(define_insn "spe_evfsctsiz" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))] - "TARGET_SPE" - "evfsctsiz %0,%1" - [(set_attr "type" "vecfloat") - (set_attr "length" "4")]) - -(define_insn "spe_evfsctuf" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") - (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))] - "TARGET_SPE" - "evfsctuf %0,%1" - [(set_attr "type" "vecfloat") - (set_attr "length" "4")]) - -(define_insn "spe_evfsctui" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))] - "TARGET_SPE" - "evfsctui %0,%1" - [(set_attr "type" "vecfloat") - (set_attr "length" "4")]) - -(define_insn "spe_evfsctuiz" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))] - "TARGET_SPE" - "evfsctuiz %0,%1" - [(set_attr "type" "vecfloat") - (set_attr "length" "4")]) - -(define_insn "spe_evfsdiv" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") - (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") - (match_operand:V2SF 2 "gpc_reg_operand" "r"))) - (clobber (reg:SI SPEFSCR_REGNO))] - "TARGET_SPE" - "evfsdiv %0,%1,%2" - [(set_attr "type" "vecfdiv") - (set_attr "length" "4")]) - -(define_insn "spe_evfsmul" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") - (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") - (match_operand:V2SF 2 "gpc_reg_operand" "r"))) - (clobber (reg:SI SPEFSCR_REGNO))] - "TARGET_SPE" - "evfsmul %0,%1,%2" - [(set_attr "type" "vecfloat") - (set_attr "length" "4")]) - -(define_insn "spe_evfsnabs" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") - (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))] - "TARGET_SPE" - "evfsnabs %0,%1" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evfsneg" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") - (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))] - "TARGET_SPE" - "evfsneg %0,%1" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evfssub" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") - (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") - (match_operand:V2SF 2 "gpc_reg_operand" "r"))) - (clobber (reg:SI SPEFSCR_REGNO))] - "TARGET_SPE" - "evfssub %0,%1,%2" - [(set_attr "type" "vecfloat") - (set_attr "length" "4")]) - -;; SPE SIMD load instructions. - -;; Only the hardware engineer who designed the SPE understands the -;; plethora of load and store instructions ;-). We have no way of -;; differentiating between them with RTL so use an unspec of const_int 0 -;; to avoid identical RTL. - -(define_insn "spe_evldd" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:QI 2 "immediate_operand" "i")))) - (unspec [(const_int 0)] 544)] - "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" - "evldd %0,%2*8(%1)" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlddx" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:SI 2 "gpc_reg_operand" "r")))) - (unspec [(const_int 0)] 545)] - "TARGET_SPE" - "evlddx %0,%1,%2" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evldh" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:QI 2 "immediate_operand" "i")))) - (unspec [(const_int 0)] 546)] - "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" - "evldh %0,%2*8(%1)" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evldhx" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:SI 2 "gpc_reg_operand" "r")))) - (unspec [(const_int 0)] 547)] - "TARGET_SPE" - "evldhx %0,%1,%2" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evldw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:QI 2 "immediate_operand" "i")))) - (unspec [(const_int 0)] 548)] - "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" - "evldw %0,%2*8(%1)" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evldwx" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:SI 2 "gpc_reg_operand" "r")))) - (unspec [(const_int 0)] 549)] - "TARGET_SPE" - "evldwx %0,%1,%2" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlwhe" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:QI 2 "immediate_operand" "i")))) - (unspec [(const_int 0)] 550)] - "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" - "evlwhe %0,%2*4(%1)" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlwhex" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:SI 2 "gpc_reg_operand" "r")))) - (unspec [(const_int 0)] 551)] - "TARGET_SPE" - "evlwhex %0,%1,%2" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlwhos" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:QI 2 "immediate_operand" "i")))) - (unspec [(const_int 0)] 552)] - "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" - "evlwhos %0,%2*4(%1)" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlwhosx" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:SI 2 "gpc_reg_operand" "r")))) - (unspec [(const_int 0)] 553)] - "TARGET_SPE" - "evlwhosx %0,%1,%2" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlwhou" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:QI 2 "immediate_operand" "i")))) - (unspec [(const_int 0)] 554)] - "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" - "evlwhou %0,%2*4(%1)" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_evlwhoux" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand:SI 2 "gpc_reg_operand" "r")))) - (unspec [(const_int 0)] 555)] - "TARGET_SPE" - "evlwhoux %0,%1,%2" - [(set_attr "type" "vecload") - (set_attr "length" "4")]) - -(define_insn "spe_brinc" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "gpc_reg_operand" "r")] 556))] - "TARGET_SPE" - "brinc %0,%1,%2" - [(set_attr "type" "brinc") - (set_attr "length" "4")]) - -(define_insn "spe_evmhegsmfaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 557)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhegsmfaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhegsmfan" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 558)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhegsmfan %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhegsmiaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 559)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhegsmiaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhegsmian" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 560)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhegsmian %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhegumiaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 561)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhegumiaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhegumian" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 562)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhegumian %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhesmfaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 563)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhesmfaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhesmfanw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 564)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhesmfanw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhesmfa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhesmfa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhesmf" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))] - "TARGET_SPE" - "evmhesmf %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhesmiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 567)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhesmiaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhesmianw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 568)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhesmianw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhesmia" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhesmia %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhesmi" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))] - "TARGET_SPE" - "evmhesmi %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhessfaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 571)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhessfaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhessfanw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 572)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhessfanw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhessfa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhessfa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhessf" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574)) - (clobber (reg:SI SPEFSCR_REGNO))] - "TARGET_SPE" - "evmhessf %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhessiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 575)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhessiaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhessianw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 576)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhessianw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmheumiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 577)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmheumiaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmheumianw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 578)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmheumianw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmheumia" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmheumia %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmheumi" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))] - "TARGET_SPE" - "evmheumi %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmheusiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 581)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmheusiaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmheusianw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 582)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmheusianw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhogsmfaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 583)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhogsmfaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhogsmfan" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 584)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhogsmfan %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhogsmiaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 585)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhogsmiaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhogsmian" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 586)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhogsmian %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhogumiaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 587)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhogumiaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhogumian" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 588)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhogumian %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhosmfaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 589)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhosmfaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhosmfanw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 590)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhosmfanw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhosmfa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))] - "TARGET_SPE" - "evmhosmfa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhosmf" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhosmf %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhosmiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 593)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhosmiaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhosmianw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 594)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhosmianw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhosmia" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhosmia %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhosmi" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))] - "TARGET_SPE" - "evmhosmi %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhossfaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 597)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhossfaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhossfanw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 598)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhossfanw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhossfa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 599)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhossfa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhossf" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600)) - (clobber (reg:SI SPEFSCR_REGNO))] - "TARGET_SPE" - "evmhossf %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhossiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 601)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhossiaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhossianw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 602)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhossianw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhoumiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 603)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhoumiaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhoumianw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 604)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhoumianw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhoumia" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhoumia %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhoumi" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))] - "TARGET_SPE" - "evmhoumi %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhousiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 607)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhousiaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmhousianw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 608)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmhousianw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmmlssfa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))] - "TARGET_SPE" - "evmmlssfa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmmlssf" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))] - "TARGET_SPE" - "evmmlssf %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhsmfa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhsmfa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhsmf" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))] - "TARGET_SPE" - "evmwhsmf %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhsmia" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhsmia %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhsmi" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))] - "TARGET_SPE" - "evmwhsmi %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhssfa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhssfa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhusian" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))] - "TARGET_SPE" - "evmwhusian %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhssf" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628)) - (clobber (reg:SI SPEFSCR_REGNO))] - "TARGET_SPE" - "evmwhssf %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhumia" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhumia %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhumi" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))] - "TARGET_SPE" - "evmwhumi %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwlsmiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 635)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwlsmiaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwlsmianw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 636)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwlsmianw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwlssiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 641)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwlssiaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwlssianw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 642)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwlssianw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwlumiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 643)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwlumiaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwlumianw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 644)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwlumianw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwlumia" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwlumia %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwlumi" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))] - "TARGET_SPE" - "evmwlumi %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwlusiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 647)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwlusiaaw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwlusianw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 648)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwlusianw %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwsmfaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 649)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwsmfaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwsmfan" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 650)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwsmfan %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwsmfa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwsmfa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwsmf" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))] - "TARGET_SPE" - "evmwsmf %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwsmiaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 653)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwsmiaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwsmian" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 654)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwsmian %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwsmia" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwsmia %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwsmi" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))] - "TARGET_SPE" - "evmwsmi %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwssfaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 657)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwssfaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwssfan" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 658)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwssfan %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwssfa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwssfa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwssf" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660)) - (clobber (reg:SI SPEFSCR_REGNO))] - "TARGET_SPE" - "evmwssf %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwumiaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 661)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwumiaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwumian" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 662)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwumian %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwumia" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwumia %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwumi" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))] - "TARGET_SPE" - "evmwumi %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "addv2si3" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")))] - "TARGET_SPE" - "evaddw %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evaddusiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 673)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evaddusiaaw %0,%1" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evaddumiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 674)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evaddumiaaw %0,%1" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evaddssiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 675)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evaddssiaaw %0,%1" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evaddsmiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 676)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evaddsmiaaw %0,%1" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evaddiw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:QI 2 "immediate_operand" "i")] 677))] - "TARGET_SPE" - "evaddiw %0,%1,%2" - [(set_attr "type" "vecsimple") - (set_attr "length" "4")]) - -(define_insn "spe_evsubifw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:QI 2 "immediate_operand" "i")] 678))] - "TARGET_SPE" - "evsubifw %0,%2,%1" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "subv2si3" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")))] - "TARGET_SPE" - "evsubfw %0,%2,%1" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evsubfusiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 679)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evsubfusiaaw %0,%1" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evsubfumiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 680)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evsubfumiaaw %0,%1" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evsubfssiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 681)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evsubfssiaaw %0,%1" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evsubfsmiaaw" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (reg:V2SI SPE_ACC_REGNO)] 682)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evsubfsmiaaw %0,%1" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmra" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (match_operand:V2SI 1 "gpc_reg_operand" "r")) - (set (reg:V2SI SPE_ACC_REGNO) - (unspec:V2SI [(match_dup 1)] 726))] - "TARGET_SPE" - "evmra %0,%1" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "divv2si3" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r"))) - (clobber (reg:SI SPEFSCR_REGNO))] - "TARGET_SPE" - "evdivws %0,%1,%2" - [(set_attr "type" "vecdiv") - (set_attr "length" "4")]) - -(define_insn "spe_evdivwu" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r"))) - (clobber (reg:SI SPEFSCR_REGNO))] - "TARGET_SPE" - "evdivwu %0,%1,%2" - [(set_attr "type" "vecdiv") - (set_attr "length" "4")]) - -(define_insn "spe_evsplatfi" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))] - "TARGET_SPE" - "evsplatfi %0,%1" - [(set_attr "type" "vecperm") - (set_attr "length" "4")]) - -(define_insn "spe_evsplati" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))] - "TARGET_SPE" - "evsplati %0,%1" - [(set_attr "type" "vecperm") - (set_attr "length" "4")]) - -(define_insn "spe_evstdd" - [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") - (match_operand:QI 1 "immediate_operand" "i"))) - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (unspec [(const_int 0)] 686)] - "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" - "evstdd %2,%1*8(%0)" - [(set_attr "type" "vecstore") - (set_attr "length" "4")]) - -(define_insn "spe_evstddx" - [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") - (match_operand:SI 1 "gpc_reg_operand" "r"))) - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (unspec [(const_int 0)] 687)] - "TARGET_SPE" - "evstddx %2,%0,%1" - [(set_attr "type" "vecstore") - (set_attr "length" "4")]) - -(define_insn "spe_evstdh" - [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") - (match_operand:QI 1 "immediate_operand" "i"))) - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (unspec [(const_int 0)] 688)] - "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" - "evstdh %2,%1*8(%0)" - [(set_attr "type" "vecstore") - (set_attr "length" "4")]) - -(define_insn "spe_evstdhx" - [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") - (match_operand:SI 1 "gpc_reg_operand" "r"))) - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (unspec [(const_int 0)] 689)] - "TARGET_SPE" - "evstdhx %2,%0,%1" - [(set_attr "type" "vecstore") - (set_attr "length" "4")]) - -(define_insn "spe_evstdw" - [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") - (match_operand:QI 1 "immediate_operand" "i"))) - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (unspec [(const_int 0)] 690)] - "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" - "evstdw %2,%1*8(%0)" - [(set_attr "type" "vecstore") - (set_attr "length" "4")]) - -(define_insn "spe_evstdwx" - [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") - (match_operand:SI 1 "gpc_reg_operand" "r"))) - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (unspec [(const_int 0)] 691)] - "TARGET_SPE" - "evstdwx %2,%0,%1" - [(set_attr "type" "vecstore") - (set_attr "length" "4")]) - -(define_insn "spe_evstwhe" - [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") - (match_operand:QI 1 "immediate_operand" "i"))) - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (unspec [(const_int 0)] 692)] - "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" - "evstwhe %2,%1*4(%0)" - [(set_attr "type" "vecstore") - (set_attr "length" "4")]) - -(define_insn "spe_evstwhex" - [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") - (match_operand:SI 1 "gpc_reg_operand" "r"))) - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (unspec [(const_int 0)] 693)] - "TARGET_SPE" - "evstwhex %2,%0,%1" - [(set_attr "type" "vecstore") - (set_attr "length" "4")]) - -(define_insn "spe_evstwho" - [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") - (match_operand:QI 1 "immediate_operand" "i"))) - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (unspec [(const_int 0)] 694)] - "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" - "evstwho %2,%1*4(%0)" - [(set_attr "type" "vecstore") - (set_attr "length" "4")]) - -(define_insn "spe_evstwhox" - [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") - (match_operand:SI 1 "gpc_reg_operand" "r"))) - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (unspec [(const_int 0)] 695)] - "TARGET_SPE" - "evstwhox %2,%0,%1" - [(set_attr "type" "vecstore") - (set_attr "length" "4")]) - -(define_insn "spe_evstwwe" - [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") - (match_operand:QI 1 "immediate_operand" "i"))) - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (unspec [(const_int 0)] 696)] - "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" - "evstwwe %2,%1*4(%0)" - [(set_attr "type" "vecstore") - (set_attr "length" "4")]) - -(define_insn "spe_evstwwex" - [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") - (match_operand:SI 1 "gpc_reg_operand" "r"))) - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (unspec [(const_int 0)] 697)] - "TARGET_SPE" - "evstwwex %2,%0,%1" - [(set_attr "type" "vecstore") - (set_attr "length" "4")]) - -(define_insn "spe_evstwwo" - [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") - (match_operand:QI 1 "immediate_operand" "i"))) - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (unspec [(const_int 0)] 698)] - "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" - "evstwwo %2,%1*4(%0)" - [(set_attr "type" "vecstore") - (set_attr "length" "4")]) - -(define_insn "spe_evstwwox" - [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") - (match_operand:SI 1 "gpc_reg_operand" "r"))) - (match_operand:V2SI 2 "gpc_reg_operand" "r")) - (unspec [(const_int 0)] 699)] - "TARGET_SPE" - "evstwwox %2,%0,%1" - [(set_attr "type" "vecstore") - (set_attr "length" "4")]) - -;; Double-precision floating point instructions. - -;; FIXME: Add o=r option. -(define_insn "*frob__" - [(set (match_operand:SPE64 0 "nonimmediate_operand" "=r,r") - (subreg:SPE64 (match_operand:DITI 1 "input_operand" "r,m") 0))] - "TARGET_SPE && mode != DFmode" -{ - switch (which_alternative) - { - default: - gcc_unreachable (); - case 0: - if (WORDS_BIG_ENDIAN) - return "evmergelo %0,%1,%L1"; - else - return "evmergelo %0,%L1,%1"; - case 1: - return "evldd%X1 %0,%y1"; - } -}) - -(define_insn "*frob__ti_8" - [(set (match_operand:SPE64 0 "nonimmediate_operand" "=r") - (subreg:SPE64 (match_operand:TI 1 "input_operand" "r") 8))] - "TARGET_SPE && mode != DFmode" -{ - if (WORDS_BIG_ENDIAN) - return "evmergelo %0,%Y1,%Z1"; - else - return "evmergelo %0,%Z1,%Y1"; -}) - -(define_insn "*frob__di_2" - [(set (subreg:DI (match_operand:SPE64TF 0 "nonimmediate_operand" "+&r,r") 0) - (match_operand:DI 1 "input_operand" "r,m"))] - "TARGET_SPE && mode != DFmode && mode != TFmode" -{ - switch (which_alternative) - { - default: - gcc_unreachable (); - case 0: - if (WORDS_BIG_ENDIAN) - return "evmergelo %0,%1,%L1"; - else - return "evmergelo %0,%L1,%1"; - case 1: - return "evldd%X1 %0,%y1"; - } -}) - -(define_insn "*frob_di_" - [(set (match_operand:DI 0 "nonimmediate_operand" "=&r") - (subreg:DI (match_operand:SPE64TF 1 "input_operand" "r") 0))] - "TARGET_SPE && mode != DFmode && mode != TFmode" -{ - if (WORDS_BIG_ENDIAN) - return "evmergehi %0,%1,%1\;mr %L0,%1"; - else - return "evmergehi %L0,%1,%1\;mr %0,%1"; -} - [(set_attr "length" "8")]) - -(define_insn "*frob___2" - [(set (subreg:SPE64 (match_operand:DITI 0 "register_operand" "+&r,r") 0) - (match_operand:SPE64 1 "input_operand" "r,m"))] - "TARGET_SPE && mode != DFmode" - "* -{ - switch (which_alternative) - { - default: - gcc_unreachable (); - case 0: - if (WORDS_BIG_ENDIAN) - return \"evmergehi %0,%1,%1\;mr %L0,%1\"; - else - return \"evmergehi %L0,%1,%1\;mr %0,%1\"; - case 1: - /* If the address is not offsettable we need to load the whole - doubleword into a 64-bit register and then copy the high word - to form the correct output layout. */ - if (!offsettable_nonstrict_memref_p (operands[1])) - { - if (WORDS_BIG_ENDIAN) - return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\"; - else - return \"evldd%X1 %0,%y1\;evmergehi %L0,%0,%0\"; - } - /* If the low-address word is used in the address, we must load - it last. Otherwise, load it first. Note that we cannot have - auto-increment in that case since the address register is - known to be dead. */ - if (refers_to_regno_p (REGNO (operands[0]), operands[1])) - { - if (WORDS_BIG_ENDIAN) - return \"lwz %L0,%L1\;lwz %0,%1\"; - else - return \"lwz %0,%1\;lwz %L0,%L1\"; - } - else - { - if (WORDS_BIG_ENDIAN) - return \"lwz%U1%X1 %0,%1\;lwz %L0,%L1\"; - else - return \"lwz%U1%X1 %L0,%L1\;lwz %0,%1\"; - } - } -}" - [(set_attr "length" "8,8")]) - -; As the above, but TImode at offset 8. -(define_insn "*frob_ti__8_2" - [(set (subreg:SPE64 (match_operand:TI 0 "register_operand" "+&r,r") 8) - (match_operand:SPE64 1 "input_operand" "r,m"))] - "TARGET_SPE && mode != DFmode" - "* -{ - switch (which_alternative) - { - default: - gcc_unreachable (); - case 0: - if (WORDS_BIG_ENDIAN) - return \"evmergehi %Y0,%1,%1\;mr %Z0,%1\"; - else - return \"evmergehi %Z0,%1,%1\;mr %Y0,%1\"; - case 1: - if (!offsettable_nonstrict_memref_p (operands[1])) - { - if (WORDS_BIG_ENDIAN) - return \"evldd%X1 %Z0,%y1\;evmergehi %Y0,%Z0,%Z0\"; - else - return \"evldd%X1 %Y0,%y1\;evmergehi %Z0,%Y0,%Y0\"; - } - if (refers_to_regno_p (REGNO (operands[0]), operands[1])) - { - if (WORDS_BIG_ENDIAN) - return \"lwz %Z0,%L1\;lwz %Y0,%1\"; - else - return \"lwz %Y0,%1\;lwz %Z0,%L1\"; - } - else - { - if (WORDS_BIG_ENDIAN) - return \"lwz%U1%X1 %Y0,%1\;lwz %Z0,%L1\"; - else - return \"lwz%U1%X1 %Z0,%L1\;lwz %Y0,%1\"; - } - } -}" - [(set_attr "length" "8,8")]) - -(define_insn "mov_si_e500_subreg0_be" - [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 0) - (match_operand:SI 1 "input_operand" "r,m"))] - "WORDS_BIG_ENDIAN - && (TARGET_SPE && mode != DFmode && mode != TFmode)" - "@ - evmergelo %0,%1,%0 - evmergelohi %0,%0,%0\;lwz%U1%X1 %0,%1\;evmergelohi %0,%0,%0" - [(set_attr "length" "4,12")]) - -(define_insn "*mov_si_e500_subreg0_le" - [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 0) - (match_operand:SI 1 "input_operand" "r,m"))] - "!WORDS_BIG_ENDIAN - && (TARGET_SPE && mode != DFmode && mode != TFmode)" - "@ - mr %0,%1 - lwz%U1%X1 %0,%1") - -(define_insn_and_split "*mov_si_e500_subreg0_elf_low_be" - [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0) - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand 2 "" "")))] - "WORDS_BIG_ENDIAN - && TARGET_SPE && mode != DFmode && mode != TFmode - && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - rtx tmp = gen_reg_rtx (SImode); - emit_insn (gen_elf_low (tmp, operands[1], operands[2])); - emit_insn (gen_mov_si_e500_subreg0_be (operands[0], tmp)); - DONE; -} - [(set_attr "length" "8")]) - -(define_insn "*mov_si_e500_subreg0_elf_low_le" - [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0) - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand 2 "" "")))] - "!WORDS_BIG_ENDIAN - && TARGET_SPE && mode != DFmode && mode != TFmode - && TARGET_ELF && !TARGET_64BIT" - "addi %0,%1,%K2") - -;; ??? Could use evstwwe for memory stores in some cases, depending on -;; the offset. -(define_insn "*mov_si_e500_subreg0_2_be" - [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m") - (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 0))] - "WORDS_BIG_ENDIAN - && TARGET_SPE && mode != DFmode && mode != TFmode" - "@ - evmergelohi %0,%1,%1 - evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0" - [(set_attr "length" "4,8")]) - -(define_insn "*mov_si_e500_subreg0_2_le" - [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m") - (subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 0))] - "!WORDS_BIG_ENDIAN - && TARGET_SPE && mode != DFmode && mode != TFmode" - "@ - mr %0,%1 - stw%U0%X0 %1,%0") - -(define_insn "*mov_si_e500_subreg4_be" - [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 4) - (match_operand:SI 1 "input_operand" "r,m"))] - "WORDS_BIG_ENDIAN - && TARGET_SPE && mode != DFmode && mode != TFmode" - "@ - mr %0,%1 - lwz%U1%X1 %0,%1") - -(define_insn "mov_si_e500_subreg4_le" - [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 4) - (match_operand:SI 1 "input_operand" "r,m"))] - "!WORDS_BIG_ENDIAN - && TARGET_SPE && mode != DFmode && mode != TFmode" - "@ - evmergelo %0,%1,%0 - evmergelohi %0,%0,%0\;lwz%U1%X1 %0,%1\;evmergelohi %0,%0,%0" - [(set_attr "length" "4,12")]) - -(define_insn "*mov_si_e500_subreg4_elf_low_be" - [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4) - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand 2 "" "")))] - "WORDS_BIG_ENDIAN - && TARGET_SPE && mode != DFmode && mode != TFmode - && TARGET_ELF && !TARGET_64BIT" - "addi %0,%1,%K2") - -(define_insn_and_split "*mov_si_e500_subreg4_elf_low_le" - [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4) - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand 2 "" "")))] - "!WORDS_BIG_ENDIAN - && TARGET_SPE && mode != DFmode && mode != TFmode - && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - rtx tmp = gen_reg_rtx (SImode); - emit_insn (gen_elf_low (tmp, operands[1], operands[2])); - emit_insn (gen_mov_si_e500_subreg4_le (operands[0], tmp)); - DONE; -} - [(set_attr "length" "8")]) - -(define_insn "*mov_si_e500_subreg4_2_be" - [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m") - (subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))] - "WORDS_BIG_ENDIAN - && TARGET_SPE && mode != DFmode && mode != TFmode" - "@ - mr %0,%1 - stw%U0%X0 %1,%0") - -(define_insn "*mov_si_e500_subreg4_2_le" - [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m") - (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 4))] - "!WORDS_BIG_ENDIAN - && TARGET_SPE && mode != DFmode && mode != TFmode" - "@ - evmergelohi %0,%1,%1 - evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0" - [(set_attr "length" "4,8")]) - -;; Vector move instructions. - -(define_expand "movv2si" - [(set (match_operand:V2SI 0 "nonimmediate_operand" "") - (match_operand:V2SI 1 "any_operand" ""))] - "TARGET_SPE" - "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }") - -(define_insn "*movv2si_internal" - [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r") - (match_operand:V2SI 1 "input_operand" "r,m,r,W"))] - "TARGET_SPE - && (gpc_reg_operand (operands[0], V2SImode) - || gpc_reg_operand (operands[1], V2SImode))" - "* -{ - switch (which_alternative) - { - case 0: return \"evstdd%X0 %1,%y0\"; - case 1: return \"evldd%X1 %0,%y1\"; - case 2: return \"evor %0,%1,%1\"; - case 3: return output_vec_const_move (operands); - default: gcc_unreachable (); - } -}" - [(set_attr "type" "vecload,vecstore,*,*") - (set_attr "length" "*,*,*,12")]) - -(define_split - [(set (match_operand:V2SI 0 "register_operand" "") - (match_operand:V2SI 1 "zero_constant" ""))] - "TARGET_SPE && reload_completed" - [(set (match_dup 0) - (xor:V2SI (match_dup 0) (match_dup 0)))] - "") - -(define_expand "movv1di" - [(set (match_operand:V1DI 0 "nonimmediate_operand" "") - (match_operand:V1DI 1 "any_operand" ""))] - "TARGET_SPE" - "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }") - -(define_insn "*movv1di_internal" - [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r") - (match_operand:V1DI 1 "input_operand" "r,m,r,W"))] - "TARGET_SPE - && (gpc_reg_operand (operands[0], V1DImode) - || gpc_reg_operand (operands[1], V1DImode))" - "@ - evstdd%X0 %1,%y0 - evldd%X1 %0,%y1 - evor %0,%1,%1 - evxor %0,%0,%0" - [(set_attr "type" "vecload,vecstore,*,*") - (set_attr "length" "*,*,*,*")]) - -(define_expand "movv4hi" - [(set (match_operand:V4HI 0 "nonimmediate_operand" "") - (match_operand:V4HI 1 "any_operand" ""))] - "TARGET_SPE" - "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }") - -(define_insn "*movv4hi_internal" - [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r,r") - (match_operand:V4HI 1 "input_operand" "r,m,r,W"))] - "TARGET_SPE - && (gpc_reg_operand (operands[0], V4HImode) - || gpc_reg_operand (operands[1], V4HImode))" - "@ - evstdd%X0 %1,%y0 - evldd%X1 %0,%y1 - evor %0,%1,%1 - evxor %0,%0,%0" - [(set_attr "type" "vecload")]) - -(define_expand "movv2sf" - [(set (match_operand:V2SF 0 "nonimmediate_operand" "") - (match_operand:V2SF 1 "any_operand" ""))] - "TARGET_SPE || TARGET_PAIRED_FLOAT" - "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }") - -(define_insn "*movv2sf_internal" - [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r") - (match_operand:V2SF 1 "input_operand" "r,m,r,W"))] - "TARGET_SPE - && (gpc_reg_operand (operands[0], V2SFmode) - || gpc_reg_operand (operands[1], V2SFmode))" - "@ - evstdd%X0 %1,%y0 - evldd%X1 %0,%y1 - evor %0,%1,%1 - evxor %0,%0,%0" - [(set_attr "type" "vecload,vecstore,*,*") - (set_attr "length" "*,*,*,*")]) - -;; End of vector move instructions. - -(define_insn "spe_evmwhssfaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhssfaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhssmaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhssmaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhsmfaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhsmfaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhsmiaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhsmiaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhusiaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhusiaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhumiaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhumiaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhssfan" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhssfan %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhssian" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhssian %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhsmfan" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhsmfan %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhsmian" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhsmian %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhumian" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhumian %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhgssfaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhgssfaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhgsmfaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhgsmfaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhgsmiaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhgsmiaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhgumiaa" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhgumiaa %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhgssfan" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718)) - (clobber (reg:SI SPEFSCR_REGNO)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhgssfan %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhgsmfan" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhgsmfan %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhgsmian" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhgsmian %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_evmwhgumian" - [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") - (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") - (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721)) - (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] - "TARGET_SPE" - "evmwhgumian %0,%1,%2" - [(set_attr "type" "veccomplex") - (set_attr "length" "4")]) - -(define_insn "spe_mtspefscr" - [(set (reg:SI SPEFSCR_REGNO) - (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] - 722))] - "TARGET_SPE" - "mtspefscr %0" - [(set_attr "type" "vecsimple")]) - -(define_insn "spe_mfspefscr" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))] - "TARGET_SPE" - "mfspefscr %0" - [(set_attr "type" "vecsimple")]) - -;; MPC8540 single-precision FP instructions on GPRs. -;; We have 2 variants for each. One for IEEE compliant math and one -;; for non IEEE compliant math. - -;; Out-of-line prologues and epilogues. -(define_insn "*save_gpregs_spe" - [(match_parallel 0 "any_parallel_operand" - [(clobber (reg:P LR_REGNO)) - (use (match_operand:P 1 "symbol_ref_operand" "s")) - (use (reg:P 11)) - (set (match_operand:V2SI 2 "memory_operand" "=m") - (match_operand:V2SI 3 "gpc_reg_operand" "r"))])] - "TARGET_SPE_ABI" - "bl %z1" - [(set_attr "type" "branch") - (set_attr "length" "4")]) - -(define_insn "*restore_gpregs_spe" - [(match_parallel 0 "any_parallel_operand" - [(clobber (reg:P LR_REGNO)) - (use (match_operand:P 1 "symbol_ref_operand" "s")) - (use (reg:P 11)) - (set (match_operand:V2SI 2 "gpc_reg_operand" "=r") - (match_operand:V2SI 3 "memory_operand" "m"))])] - "TARGET_SPE_ABI" - "bl %z1" - [(set_attr "type" "branch") - (set_attr "length" "4")]) - -(define_insn "*return_and_restore_gpregs_spe" - [(match_parallel 0 "any_parallel_operand" - [(return) - (clobber (reg:P LR_REGNO)) - (use (match_operand:P 1 "symbol_ref_operand" "s")) - (use (reg:P 11)) - (set (match_operand:V2SI 2 "gpc_reg_operand" "=r") - (match_operand:V2SI 3 "memory_operand" "m"))])] - "TARGET_SPE_ABI" - "b %z1" - [(set_attr "type" "branch") - (set_attr "length" "4")]) diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index ea8169fabe0..a3d53e7f439 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -1309,98 +1309,3 @@ emit_insn (gen_vsx_extract_ (operand0, vec, elt)); DONE; }) - - -;;; Expanders for vector insn patterns shared between the SPE and TARGET_PAIRED systems. - -(define_expand "absv2sf2" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "") - (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))] - "TARGET_PAIRED_FLOAT || TARGET_SPE" - "") - -(define_expand "negv2sf2" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "") - (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))] - "TARGET_PAIRED_FLOAT || TARGET_SPE" - "") - -(define_expand "addv2sf3" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "") - (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "") - (match_operand:V2SF 2 "gpc_reg_operand" "")))] - "TARGET_PAIRED_FLOAT || TARGET_SPE" - " -{ - if (TARGET_SPE) - { - /* We need to make a note that we clobber SPEFSCR. */ - rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); - - XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0], - gen_rtx_PLUS (V2SFmode, operands[1], operands[2])); - XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO)); - emit_insn (par); - DONE; - } -}") - -(define_expand "subv2sf3" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "") - (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "") - (match_operand:V2SF 2 "gpc_reg_operand" "")))] - "TARGET_PAIRED_FLOAT || TARGET_SPE" - " -{ - if (TARGET_SPE) - { - /* We need to make a note that we clobber SPEFSCR. */ - rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); - - XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0], - gen_rtx_MINUS (V2SFmode, operands[1], operands[2])); - XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO)); - emit_insn (par); - DONE; - } -}") - -(define_expand "mulv2sf3" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "") - (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "") - (match_operand:V2SF 2 "gpc_reg_operand" "")))] - "TARGET_PAIRED_FLOAT || TARGET_SPE" - " -{ - if (TARGET_SPE) - { - /* We need to make a note that we clobber SPEFSCR. */ - rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); - - XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0], - gen_rtx_MULT (V2SFmode, operands[1], operands[2])); - XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO)); - emit_insn (par); - DONE; - } -}") - -(define_expand "divv2sf3" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "") - (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "") - (match_operand:V2SF 2 "gpc_reg_operand" "")))] - "TARGET_PAIRED_FLOAT || TARGET_SPE" - " -{ - if (TARGET_SPE) - { - /* We need to make a note that we clobber SPEFSCR. */ - rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); - - XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0], - gen_rtx_DIV (V2SFmode, operands[1], operands[2])); - XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO)); - emit_insn (par); - DONE; - } -}")