From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 5 Oct 2015 04:24:32 +0000 (+0800)
Subject: sim: make sure replaced memory signals are always in VCD signal set
X-Git-Tag: 24jan2021_ls180~2099^2~3^2~25
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e0899c1424ccc04ad161fbe9b7107c7d6373d98f;p=litex.git

sim: make sure replaced memory signals are always in VCD signal set
---

diff --git a/migen/sim/core.py b/migen/sim/core.py
index d531ee90..3329e8e3 100644
--- a/migen/sim/core.py
+++ b/migen/sim/core.py
@@ -237,6 +237,8 @@ class Simulator:
                 signals.add(cd.clk)
                 if cd.rst is not None:
                     signals.add(cd.rst)
+            for memory_array in mta.replacements.values():
+                signals |= set(memory_array)
             signals = sorted(signals, key=lambda x: x.duid)
             self.vcd = VCDWriter(vcd_name, signals)