From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 3 May 2019 15:06:16 +0000 (-0700)
Subject: If init is 1'bx, do not add to dict as per @cliffordwolf
X-Git-Tag: yosys-0.9~156^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e08df0c7390e1e7736c3d5b0abbe2679bf9b4518;p=yosys.git

If init is 1'bx, do not add to dict as per @cliffordwolf
---

diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc
index 48390488e..0ad33dc0e 100644
--- a/passes/techmap/dffinit.cc
+++ b/passes/techmap/dffinit.cc
@@ -102,7 +102,8 @@ struct DffinitPass : public Pass {
 				if (wire->attributes.count("\\init")) {
 					Const value = wire->attributes.at("\\init");
 					for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
-						init_bits[sigmap(SigBit(wire, i))] = value[i];
+						if (value[i] != State::Sx)
+							init_bits[sigmap(SigBit(wire, i))] = value[i];
 				}
 				if (wire->port_output)
 					for (auto bit : sigmap(wire))