From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 31 Jul 2020 06:58:30 +0000 (+0200)
Subject: cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with... 
X-Git-Tag: 24jan2021_ls180~40
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e0a763e534ccbe8689c62906f59f5f9ebfbc27ed;p=litex.git

cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache.
---

diff --git a/litex/soc/cores/cpu/vexriscv/system.h b/litex/soc/cores/cpu/vexriscv/system.h
index 0683b5b7..f441a197 100644
--- a/litex/soc/cores/cpu/vexriscv/system.h
+++ b/litex/soc/cores/cpu/vexriscv/system.h
@@ -3,12 +3,17 @@
 
 #include <csr-defs.h>
 
+#include <generated/soc.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 __attribute__((unused)) static void flush_cpu_icache(void)
 {
+#if defined(CONFIG_CPU_VARIANT_MIN)
+  /* No instruction cache */
+#else
   asm volatile(
     ".word(0x100F)\n"
     "nop\n"
@@ -17,19 +22,22 @@ __attribute__((unused)) static void flush_cpu_icache(void)
     "nop\n"
     "nop\n"
   );
+#endif
 }
 
 __attribute__((unused)) static void flush_cpu_dcache(void)
 {
+#if defined(CONFIG_CPU_VARIANT_MIN) || defined(CONFIG_CPU_VARIANT_LITE)
+  /* No data cache */
+#else
   asm volatile(".word(0x500F)\n");
+#endif
 }
 
 void flush_l2_cache(void);
 
 void busy_wait(unsigned int ms);
 
-#include <csr-defs.h>
-
 #define csrr(reg) ({ unsigned long __tmp; \
   asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
   __tmp; })