From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 27 Jan 2020 20:30:39 +0000 (-0800)
Subject: Fix typo
X-Git-Tag: working-ls180~822^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e0bdf5d7a9280c9f975a34fc265793de86fd9bec;p=yosys.git

Fix typo
---

diff --git a/README.md b/README.md
index 043e772ba..09429cbe0 100644
--- a/README.md
+++ b/README.md
@@ -378,7 +378,7 @@ Verilog Attributes and non-standard features
   port. It can be used, for example, to specify the clk-to-Q delay of a flip-
   flop output for consideration during `abc9` techmapping.
 
-- The input port attribute ``abc9_requiredl`` specifies an integer, or a string
+- The input port attribute ``abc9_required`` specifies an integer, or a string
   of space-separated integers to be used as the required time of this blackbox
   port. It can be used, for example, to specify the setup-time of a flip-flop
   input for consideration during `abc9` techmapping.