From: Jan Beulich <jbeulich@novell.com>
Date: Fri, 1 Jun 2018 06:38:36 +0000 (+0200)
Subject: x86: tighten condition for emitting LOCK on control register accesses
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e0c7f900259ee54a6fdbc5d4103f30209dbec1bc;p=binutils-gdb.git

x86: tighten condition for emitting LOCK on control register accesses

The control register is never expressed by REX.B; this bit only affects
the involved GPR. Also only one of the operands can have its "control"
flag set, so only check the correct operand.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 14f03bc8107..199a48d8303 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2018-06-01  Jan Beulich  <jbeulich@suse.com>
+
+	* config/tc-i386.c (build_modrm_byte): Drop REX_B from condition
+	checking for the need of emitting LOCK. Check "control" bit just
+	once.
+
 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 
 	*  testsuite/gas/i386/invpcid.s,
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 36e42eb394c..3d04a8361d9 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6894,12 +6894,11 @@ build_modrm_byte (void)
 	  if ((i.op[source].regs->reg_flags & RegVRex) != 0)
 	    i.vrex |= REX_R;
 	}
-      if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
+      if (flag_code != CODE_64BIT && (i.rex & REX_R))
 	{
-	  if (!i.types[0].bitfield.control
-	      && !i.types[1].bitfield.control)
+	  if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
 	    abort ();
-	  i.rex &= ~(REX_R | REX_B);
+	  i.rex &= ~REX_R;
 	  add_prefix (LOCK_PREFIX_OPCODE);
 	}
     }