From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 25 Apr 2017 08:57:34 +0000 (+0200)
Subject: test/test_gearbox: continue, but we are hitting a simulator bug (related to clock... 
X-Git-Tag: 24jan2021_ls180~1858
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e0ce485a17e6f4265c1c2709cebde45b84a9f57d;p=litex.git

test/test_gearbox: continue, but we are hitting a simulator bug (related to clock domains declared in modules)
---

diff --git a/test/test_gearbox.py b/test/test_gearbox.py
index 5e4c7863..c8ecfad6 100644
--- a/test/test_gearbox.py
+++ b/test/test_gearbox.py
@@ -12,22 +12,32 @@ from litex.gen.genlib.cdc import Gearbox
 # compare input data to output data, should be similar
 # various datawidth/clock ratios
 
-def source_generator(dut):
-    yield
-
 
-def sink_generator(duc):
+def data_generator(dut):
+    for i in range(256):
+        yield dut.i.eq(i)
+        yield
     yield
 
+@passive
+def data_checker(dut):
+    while True:
+        #print((yield dut.o))
+        yield
+
 
 class GearboxDUT(Module):
     def __init__(self):
-        self.submodules.gearbox_down = Gearbox(10, "slow", 8, "fast")
-        self.submodules.gearbox_up = Gearbox(8, "fast", 10, "slow")
+        self.submodules.gearbox_down = Gearbox(10, "user", 8, "gearbox")
+        self.submodules.gearbox_up = Gearbox(8, "gearbox", 10, "user")
         self.comb += self.gearbox_up.i.eq(self.gearbox_down.o)
         self.i, self.o = self.gearbox_down.i, self.gearbox_up.o
 
 
 class TestGearbox(unittest.TestCase):
     def test_gearbox(self):
+        dut = GearboxDUT()
+        generators = {"user": [data_generator(dut), data_checker(dut)]}
+        clocks = {"user": 12.5, "gearbox": 10}
+        run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
         self.assertEqual(0, 0)