From: Ali Saidi <saidi@eecs.umich.edu>
Date: Sat, 12 Mar 2005 00:34:43 +0000 (-0500)
Subject: Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5
X-Git-Tag: m5_1.0_tutorial~75^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e0d52f56e12d5ef4ddbc98b173543a95f75fb68e;p=gem5.git

Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5

--HG--
rename : objects/Pci.mpy => python/m5/objects/Pci.mpy
extra : convert_revision : 6902e8f9c2a309eb1846094a94b38018587a3761
---

e0d52f56e12d5ef4ddbc98b173543a95f75fb68e
diff --cc python/m5/objects/Pci.mpy
index caa3c52ff,000000000..907472727
mode 100644,000000..100644
--- a/python/m5/objects/Pci.mpy
+++ b/python/m5/objects/Pci.mpy
@@@ -1,52 -1,0 +1,50 @@@
 +from Device import FooPioDevice, DmaDevice
 +
- simobj PciConfigData(FooPioDevice):
++simobj PciConfigData(SimObject):
 +    type = 'PciConfigData'
-     addr = 0xffffffffffffffffL
 +    VendorID = Param.UInt16("Vendor ID")
 +    DeviceID = Param.UInt16("Device ID")
 +    Command = Param.UInt16(0, "Command")
 +    Status = Param.UInt16(0, "Status")
 +    Revision = Param.UInt8(0, "Device")
 +    ProgIF = Param.UInt8(0, "Programming Interface")
 +    SubClassCode = Param.UInt8(0, "Sub-Class Code")
 +    ClassCode = Param.UInt8(0, "Class Code")
 +    CacheLineSize = Param.UInt8(0, "System Cacheline Size")
 +    LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
 +    HeaderType = Param.UInt8(0, "PCI Header Type")
 +    BIST = Param.UInt8(0, "Built In Self Test")
 +
 +    BAR0 = Param.UInt32(0x00, "Base Address Register 0")
 +    BAR1 = Param.UInt32(0x00, "Base Address Register 1")
 +    BAR2 = Param.UInt32(0x00, "Base Address Register 2")
 +    BAR3 = Param.UInt32(0x00, "Base Address Register 3")
 +    BAR4 = Param.UInt32(0x00, "Base Address Register 4")
 +    BAR5 = Param.UInt32(0x00, "Base Address Register 5")
 +    BAR0Size = Param.UInt32(0, "Base Address Register 0 Size")
 +    BAR1Size = Param.UInt32(0, "Base Address Register 1 Size")
 +    BAR2Size = Param.UInt32(0, "Base Address Register 2 Size")
 +    BAR3Size = Param.UInt32(0, "Base Address Register 3 Size")
 +    BAR4Size = Param.UInt32(0, "Base Address Register 4 Size")
 +    BAR5Size = Param.UInt32(0, "Base Address Register 5 Size")
 +
 +    CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
 +    SubsystemID = Param.UInt16(0x00, "Subsystem ID")
 +    SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
 +    ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
 +    InterruptLine = Param.UInt8(0x00, "Interrupt Line")
 +    InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
 +    MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
 +    MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
 +
 +simobj PciConfigAll(FooPioDevice):
 +    type = 'PciConfigAll'
 +
 +simobj PciDevice(DmaDevice):
 +    type = 'PciDevice'
 +    abstract = True
 +    pci_bus = Param.Int("PCI bus")
 +    pci_dev = Param.Int("PCI device number")
 +    pci_func = Param.Int("PCI function code")
 +    configdata = Param.PciConfigData(Super, "PCI Config data")
 +    configspace = Param.PciConfigAll(Super, "PCI Configspace")
-     addr = 0xffffffffffffffffL