From: Florent Kermarrec Date: Wed, 16 Mar 2016 16:44:33 +0000 (+0100) Subject: soc: replace all Sink/Source with stream.Endpoint X-Git-Tag: 24jan2021_ls180~1994 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e0e2427795f1757feb1a9de1874acad13257bfc0;p=litex.git soc: replace all Sink/Source with stream.Endpoint --- diff --git a/litex/soc/cores/uart/core.py b/litex/soc/cores/uart/core.py index fba23dcd..a3448aac 100644 --- a/litex/soc/cores/uart/core.py +++ b/litex/soc/cores/uart/core.py @@ -4,12 +4,12 @@ from litex.gen.genlib.cdc import MultiReg from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr_eventmanager import * -from litex.soc.interconnect.stream import Source, Sink, SyncFIFO, AsyncFIFO +from litex.soc.interconnect import stream class RS232PHYRX(Module): def __init__(self, pads, tuning_word): - self.source = Source([("data", 8)]) + self.source = stream.Endpoint([("data", 8)]) # # # @@ -61,7 +61,7 @@ class RS232PHYRX(Module): class RS232PHYTX(Module): def __init__(self, pads, tuning_word): - self.sink = Sink([("data", 8)]) + self.sink = stream.Endpoint([("data", 8)]) # # # @@ -113,8 +113,8 @@ class RS232PHY(Module, AutoCSR): class RS232PHYModel(Module): def __init__(self, pads): - self.sink = Sink([("data", 8)]) - self.source = Source([("data", 8)]) + self.sink = stream.Endpoint([("data", 8)]) + self.source = stream.Endpoint([("data", 8)]) self.comb += [ pads.source_stb.eq(self.sink.stb), @@ -129,10 +129,10 @@ class RS232PHYModel(Module): def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"): if sink_cd != source_cd: - fifo = AsyncFIFO([("data", 8)], depth) + fifo = stream.AsyncFIFO([("data", 8)], depth) return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo) else: - return SyncFIFO([("data", 8)], depth) + return stream.SyncFIFO([("data", 8)], depth) class UART(Module, AutoCSR): diff --git a/litex/soc/interconnect/dma_lasmi.py b/litex/soc/interconnect/dma_lasmi.py index 1d1e9998..a8592962 100644 --- a/litex/soc/interconnect/dma_lasmi.py +++ b/litex/soc/interconnect/dma_lasmi.py @@ -1,11 +1,12 @@ from litex.gen import * from litex.gen.genlib.fifo import SyncFIFO +from litex.soc.interconnect import stream class Reader(Module): def __init__(self, lasmim, fifo_depth=None): - self.address = Sink([("a", lasmim.aw)]) - self.data = Source([("d", lasmim.dw)]) + self.address = stream.Endpoint([("a", lasmim.aw)]) + self.data = stream.Endpoint([("d", lasmim.dw)]) self.busy = Signal() ### @@ -59,7 +60,7 @@ class Reader(Module): class Writer(Module): def __init__(self, lasmim, fifo_depth=None): - self.address_data = Sink([("a", lasmim.aw), ("d", lasmim.dw)]) + self.address_data = stream.Endpoint([("a", lasmim.aw), ("d", lasmim.dw)]) self.busy = Signal() ### diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py index f9a3bf33..72f5c8cf 100644 --- a/litex/soc/interconnect/stream.py +++ b/litex/soc/interconnect/stream.py @@ -53,13 +53,6 @@ class Endpoint(Record): return getattr(object.__getattribute__(self, "param"), name) -class Source(Endpoint): - pass - -class Sink(Endpoint): - pass - - class _FIFOWrapper(Module): def __init__(self, fifo_class, layout, depth): self.sink = Endpoint(layout) @@ -429,8 +422,8 @@ class PipelinedActor(BinaryActor): class Buffer(PipelinedActor): def __init__(self, layout): - self.sink = Sink(layout) - self.source = Source(layout) + self.sink = Endpoint(layout) + self.source = Endpoint(layout) PipelinedActor.__init__(self, 1) self.sync += \ If(self.pipe_ce, @@ -441,8 +434,8 @@ class Buffer(PipelinedActor): class Cast(CombinatorialActor): def __init__(self, layout_from, layout_to, reverse_from=False, reverse_to=False): - self.sink = Sink(_rawbits_layout(layout_from)) - self.source = Source(_rawbits_layout(layout_to)) + self.sink = Endpoint(_rawbits_layout(layout_from)) + self.source = Endpoint(_rawbits_layout(layout_to)) CombinatorialActor.__init__(self) # # # @@ -460,10 +453,10 @@ class Cast(CombinatorialActor): class Unpack(Module): def __init__(self, n, layout_to, reverse=False): - self.source = source = Source(layout_to) + self.source = source = Endpoint(layout_to) description_from = copy(source.description) description_from.payload_layout = pack_layout(description_from.payload_layout, n) - self.sink = sink = Sink(description_from) + self.sink = sink = Endpoint(description_from) self.busy = Signal() @@ -501,10 +494,10 @@ class Unpack(Module): class Pack(Module): def __init__(self, layout_from, n, reverse=False): - self.sink = sink = Sink(layout_from) + self.sink = sink = Endpoint(layout_from) description_to = copy(sink.description) description_to.payload_layout = pack_layout(description_to.payload_layout, n) - self.source = source = Source(description_to) + self.source = source = Endpoint(description_to) self.busy = Signal() # # # diff --git a/litex/soc/interconnect/stream_packet.py b/litex/soc/interconnect/stream_packet.py index 1eb3b207..9bfd7e5a 100644 --- a/litex/soc/interconnect/stream_packet.py +++ b/litex/soc/interconnect/stream_packet.py @@ -3,7 +3,7 @@ from litex.gen.genlib.roundrobin import * from litex.gen.genlib.record import * from litex.gen.genlib.fsm import FSM, NextState -from litex.soc.interconnect.stream import * +from litex.soc.interconnect import stream # TODO: clean up code below # XXX @@ -155,8 +155,8 @@ class Header: class Packetizer(Module): def __init__(self, sink_description, source_description, header): - self.sink = sink = Sink(sink_description) - self.source = source = Source(source_description) + self.sink = sink = stream.Endpoint(sink_description) + self.source = source = stream.Endpoint(source_description) self.header = Signal(header.length*8) # # # @@ -244,8 +244,8 @@ class Packetizer(Module): class Depacketizer(Module): def __init__(self, sink_description, source_description, header): - self.sink = sink = Sink(sink_description) - self.source = source = Source(source_description) + self.sink = sink = stream.Endpoint(sink_description) + self.source = source = stream.Endpoint(source_description) self.header = Signal(header.length*8) # # # @@ -327,8 +327,8 @@ class Depacketizer(Module): class Buffer(Module): def __init__(self, description, data_depth, cmd_depth=4, almost_full=None): - self.sink = sink = Sink(description) - self.source = source = Source(description) + self.sink = sink = stream.Endpoint(description) + self.source = source = stream.Endpoint(description) # # # diff --git a/litex/soc/interconnect/stream_sim.py b/litex/soc/interconnect/stream_sim.py index 786418c4..242a7f59 100644 --- a/litex/soc/interconnect/stream_sim.py +++ b/litex/soc/interconnect/stream_sim.py @@ -3,7 +3,7 @@ import math from copy import deepcopy from litex.gen import * -from litex.soc.interconnect.stream import Sink, Source +from litex.soc.interconnect import stream # TODO: clean up code below # XXX @@ -96,7 +96,7 @@ class Packet(list): class PacketStreamer(Module): def __init__(self, description, last_be=None): - self.source = Source(description) + self.source = stream.Endpoint(description) self.last_be = last_be # # # @@ -141,7 +141,7 @@ class PacketStreamer(Module): class PacketLogger(Module): def __init__(self, description): - self.sink = Sink(description) + self.sink = stream.Endpoint(description) # # # @@ -171,8 +171,8 @@ class AckRandomizer(Module): def __init__(self, description, level=0): self.level = level - self.sink = Sink(description) - self.source = Source(description) + self.sink = stream.Endpoint(description) + self.source = stream.Endpoint(description) self.run = Signal()