From: Zachary Snow <zach@zachjs.com>
Date: Wed, 29 Dec 2021 17:38:55 +0000 (-0700)
Subject: fix iverilog compatibility for new case expr tests
X-Git-Tag: yosys-0.13~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e0e4dfb55ea1812521aa4c0e79240987653538da;p=yosys.git

fix iverilog compatibility for new case expr tests
---

diff --git a/tests/simple/case_expr_extend.sv b/tests/simple/case_expr_extend.sv
index 61bd14df1..d4ca2aa9b 100644
--- a/tests/simple/case_expr_extend.sv
+++ b/tests/simple/case_expr_extend.sv
@@ -1,7 +1,7 @@
 module top(
     output logic [5:0] out
 );
-always_comb begin
+initial begin
     out = '0;
     case (1'b1 << 1)
         2'b10: out = '1;
diff --git a/tests/simple/case_expr_query.sv b/tests/simple/case_expr_query.sv
index 63a0a8b7a..844dfb713 100644
--- a/tests/simple/case_expr_query.sv
+++ b/tests/simple/case_expr_query.sv
@@ -1,7 +1,7 @@
 module top(
     output logic [5:0] out
 );
-always_comb begin
+initial begin
     out = '0;
     case ($bits (out)) 6:
     case ($size (out)) 6: