From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 4 Aug 2020 11:49:50 +0000 (+0200)
Subject: cores/uart: add txempty/rxfull CSRs.
X-Git-Tag: 24jan2021_ls180~33
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e0f131a317b93f212d3739905aef8a0d603164bf;p=litex.git

cores/uart: add txempty/rxfull CSRs.

Useful in some use cases, like flushing tx.
---

diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index 201fdbb6..7ae71cf4 100644
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -201,6 +201,9 @@ class UART(Module, AutoCSR, UARTInterface):
         self.ev.rx = EventSourceProcess()
         self.ev.finalize()
 
+        self._txempty = CSRStatus()
+        self._rxfull  = CSRStatus()
+
         # # #
 
         UARTInterface.__init__(self)
@@ -220,6 +223,7 @@ class UART(Module, AutoCSR, UARTInterface):
             tx_fifo.sink.valid.eq(self._rxtx.re),
             tx_fifo.sink.data.eq(self._rxtx.r),
             self._txfull.status.eq(~tx_fifo.sink.ready),
+            self._txempty.status.eq(~tx_fifo.source.valid),
             tx_fifo.source.connect(self.source),
             # Generate TX IRQ when tx_fifo becomes non-full
             self.ev.tx.trigger.eq(~tx_fifo.sink.ready)
@@ -232,6 +236,7 @@ class UART(Module, AutoCSR, UARTInterface):
         self.comb += [
             self.sink.connect(rx_fifo.sink),
             self._rxempty.status.eq(~rx_fifo.source.valid),
+            self._rxfull.status.eq(~rx_fifo.sink.ready),
             self._rxtx.w.eq(rx_fifo.source.data),
             rx_fifo.source.ready.eq(self.ev.rx.clear | (rx_fifo_rx_we & self._rxtx.we)),
             # Generate RX IRQ when rx_fifo becomes non-empty