From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Apr 2021 21:07:12 +0000 (+0100)
Subject: 4k SRAM Instance needs write-enable @ 8-bit width
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e10241839b1c678c0f0ab743095f163ed2c42454;p=soc.git

4k SRAM Instance needs write-enable @ 8-bit width
---

diff --git a/src/soc/bus/SPBlock512W64B8W.py b/src/soc/bus/SPBlock512W64B8W.py
index 02c4760c..b86a78b3 100644
--- a/src/soc/bus/SPBlock512W64B8W.py
+++ b/src/soc/bus/SPBlock512W64B8W.py
@@ -38,7 +38,7 @@ class SPBlock512W64B8W(Elaboratable):
 
         # 4k SRAM instance
         a = Signal(9)
-        we = Signal()
+        we = Signal(8) # 8 select lines
         q = Signal(64) # output
         d = Signal(64) # input