From: Luke Kenneth Casson Leighton Date: Mon, 26 Nov 2018 02:54:25 +0000 (+0000) Subject: add csr_is_valid X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e103247b196ca128bfbf4b4c6c0d68e63e64b98b;p=rv32.git add csr_is_valid --- diff --git a/cpu.py b/cpu.py index 8baa0be..c8dafde 100644 --- a/cpu.py +++ b/cpu.py @@ -328,72 +328,38 @@ class CPU(Module): s.append(i) return s - """ - function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes); - begin - case(csr_number) - `csr_ustatus, - `csr_fflags, - `csr_frm, - `csr_fcsr, - `csr_uie, - `csr_utvec, - `csr_uscratch, - `csr_uepc, - `csr_ucause, - `csr_utval, - `csr_uip, - `csr_sstatus, - `csr_sedeleg, - `csr_sideleg, - `csr_sie, - `csr_stvec, - `csr_scounteren, - `csr_sscratch, - `csr_sepc, - `csr_scause, - `csr_stval, - `csr_sip, - `csr_satp, - `csr_medeleg, - `csr_mideleg, - `csr_dcsr, - `csr_dpc, - `csr_dscratch: - get_csr_op_is_valid = 0; - `csr_cycle, - `csr_time, - `csr_instret, - `csr_cycleh, - `csr_timeh, - `csr_instreth, - `csr_mvendorid, - `csr_marchid, - `csr_mimpid, - `csr_mhartid: - get_csr_op_is_valid = ~csr_writes; - `csr_misa, - `csr_mstatus, - `csr_mie, - `csr_mtvec, - `csr_mscratch, - `csr_mepc, - `csr_mcause, - `csr_mip: - get_csr_op_is_valid = 1; - `csr_mcounteren, - `csr_mtval, - `csr_mcycle, - `csr_minstret, - `csr_mcycleh, - `csr_minstreth: - // TODO: CSRs not implemented yet - get_csr_op_is_valid = 0; - endcase - end - endfunction - - """ + def get_csr_op_is_valid(self, csr_op_is_valid, csr_number, + csr_reads, csr_writes): + """ determines if a CSR is valid + """ + c = {} + # invalid csrs + for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr, + csr_uie, csr_utvec, csr_uscratch, csr_uepc, + csr_ucause, csr_utval, csr_uip, csr_sstatus, + csr_sedeleg, csr_sideleg, csr_sie, csr_stvec, + csr_scounteren, csr_sscratch, csr_sepc, csr_scause, + csr_stval, csr_sip, csr_satp, csr_medeleg, + csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]: + c[f] = csr_op_is_valid.eq(0) + + # not-writeable -> ok + for f in [csr_cycle, csr_time, csr_instret, csr_cycleh, + csr_timeh, csr_instreth, csr_mvendorid, csr_marchid, + csr_mimpid, csr_mhartid]: + c[f] = csr_op_is_valid.eq(~csr_writes) + + # valid csrs + for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec, + csr_mscratch, csr_mepc, csr_mcause, csr_mip]: + c[f] = csr_op_is_valid.eq(1) + + # not implemented / default + for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret, + csr_mcycleh, csr_minstreth, "default"]: + c[f] = csr_op_is_valid.eq(0) + + return Case(csr_number, c) def __init__(self): self.clk = ClockSignal() @@ -653,6 +619,8 @@ class CPU(Module): self.comb += csr_reads.eq(dc.funct3[1] | (dc.rd != 0)) self.comb += csr_writes.eq(~dc.funct3[1] | (dc.rs1 != 0)) + self.comb += self.get_csr_op_is_valid(csr_op_is_valid, csr_number, + csr_reads, csr_writes) if __name__ == "__main__": example = CPU() @@ -669,72 +637,6 @@ if __name__ == "__main__": """ - function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes); - begin - case(csr_number) - `csr_ustatus, - `csr_fflags, - `csr_frm, - `csr_fcsr, - `csr_uie, - `csr_utvec, - `csr_uscratch, - `csr_uepc, - `csr_ucause, - `csr_utval, - `csr_uip, - `csr_sstatus, - `csr_sedeleg, - `csr_sideleg, - `csr_sie, - `csr_stvec, - `csr_scounteren, - `csr_sscratch, - `csr_sepc, - `csr_scause, - `csr_stval, - `csr_sip, - `csr_satp, - `csr_medeleg, - `csr_mideleg, - `csr_dcsr, - `csr_dpc, - `csr_dscratch: - get_csr_op_is_valid = 0; - `csr_cycle, - `csr_time, - `csr_instret, - `csr_cycleh, - `csr_timeh, - `csr_instreth, - `csr_mvendorid, - `csr_marchid, - `csr_mimpid, - `csr_mhartid: - get_csr_op_is_valid = ~csr_writes; - `csr_misa, - `csr_mstatus, - `csr_mie, - `csr_mtvec, - `csr_mscratch, - `csr_mepc, - `csr_mcause, - `csr_mip: - get_csr_op_is_valid = 1; - `csr_mcounteren, - `csr_mtval, - `csr_mcycle, - `csr_minstret, - `csr_mcycleh, - `csr_minstreth: - // TODO: CSRs not implemented yet - get_csr_op_is_valid = 0; - endcase - end - endfunction - - assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes); - wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter wire [63:0] time_counter = 0; // TODO: implement time_counter wire [63:0] instret_counter = 0; // TODO: implement instret_counter