From: Alyssa Rosenzweig Date: Thu, 1 Aug 2019 21:06:19 +0000 (-0700) Subject: pan/midgard: Decode register/component in load/store argument X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e112d9d333e72d5aa304cf1de1b5b245f68acccc;p=mesa.git pan/midgard: Decode register/component in load/store argument 3-bits out of 8 down! Signed-off-by: Alyssa Rosenzweig --- diff --git a/src/panfrost/midgard/disassemble.c b/src/panfrost/midgard/disassemble.c index b9740caa1b8..4cfb281b714 100644 --- a/src/panfrost/midgard/disassemble.c +++ b/src/panfrost/midgard/disassemble.c @@ -971,7 +971,14 @@ is_op_varying(unsigned op) static void print_load_store_arg(uint8_t arg) { - printf("0x%X", arg); + /* Try to interpret as a register */ + midgard_ldst_register_select sel; + memcpy(&sel, &arg, sizeof(arg)); + + unsigned reg = REGISTER_LDST_BASE + sel.select; + char comp = components[sel.component]; + + printf("r%d.%c /* 0x%X */", reg, comp, arg); } static void diff --git a/src/panfrost/midgard/midgard.h b/src/panfrost/midgard/midgard.h index 45eaca21c42..8a71934a683 100644 --- a/src/panfrost/midgard/midgard.h +++ b/src/panfrost/midgard/midgard.h @@ -498,6 +498,20 @@ __attribute__((__packed__)) } midgard_varying_parameter; +/* 8-bit register/etc selector for load/store ops */ +typedef struct +__attribute__((__packed__)) +{ + /* Indexes into the register */ + unsigned component : 2; + + /* Register select between r26/r27 */ + unsigned select : 1; + + unsigned unknown : 5; +} +midgard_ldst_register_select; + typedef struct __attribute__((__packed__)) { @@ -510,7 +524,8 @@ __attribute__((__packed__)) * these are limited to load/store registers with only a few supported * mask/swizzle combinations. The tradeoff is these are much more * compact, requiring 8-bits each rather than 17-bits for a full - * reg/mask/swizzle */ + * reg/mask/swizzle. Usually (?) encoded as + * midgard_ldst_register_select. */ unsigned arg_1 : 8; unsigned arg_2 : 8;