From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Mon, 13 Feb 2012 22:11:16 +0000 (+0100)
Subject: bus/wishbone2asmi: cache hits working
X-Git-Tag: 24jan2021_ls180~2099^2~1022
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e11d9b9322f20145c54b8eab3ad9b666ac37e72a;p=litex.git

bus/wishbone2asmi: cache hits working
---

diff --git a/migen/bus/wishbone2asmi.py b/migen/bus/wishbone2asmi.py
index 64c306f9..c7f35043 100644
--- a/migen/bus/wishbone2asmi.py
+++ b/migen/bus/wishbone2asmi.py
@@ -61,15 +61,15 @@ class WB2ASMI:
 				data_we.eq(Replicate(1, adw//8))
 			).Else(
 				data_di.eq(Replicate(self.wishbone.dat_i, adw//32)),
-				If(self.wishbone.cyc_i & self.wishbone.stb_i & self.wishbone.ack_o,
-					displacer(self.wishbone.we_i, adr_offset, data_we, 2**offsetbits)
+				If(self.wishbone.cyc_i & self.wishbone.stb_i & self.wishbone.we_i & self.wishbone.ack_o,
+					displacer(self.wishbone.sel_i, adr_offset, data_we, 2**offsetbits, reverse=True)
 				)
 			),
 			If(write_to_asmi,
 				self.asmiport.dat_w.eq(data_do),
 				self.asmiport.dat_wm.eq(Replicate(1, adw//8))
 			),
-			chooser(data_do, adr_offset_r, self.wishbone.dat_o)
+			chooser(data_do, adr_offset_r, self.wishbone.dat_o, reverse=True)
 		]
 		sync += [
 			adr_offset_r.eq(adr_offset)