From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 22 May 2015 06:20:29 +0000 (+0200)
Subject: preserve used $-wires with init attribute in opt_clean
X-Git-Tag: yosys-0.6~285
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e122c2644e4bbcb9384c7f0b65c69cc9671698dd;p=yosys.git

preserve used $-wires with init attribute in opt_clean
---

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 9d2a262a1..a34da781a 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -216,7 +216,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 	std::vector<RTLIL::Wire*> maybe_del_wires;
 	for (auto wire : module->wires())
 	{
-		if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep")) {
+		if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep") || wire->attributes.count("\\init")) {
 			RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1;
 			assign_map.apply(s2);
 			if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) {