From: lkcl <lkcl@web>
Date: Fri, 6 Aug 2021 14:47:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~474
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e1274e8f7b8c37560fd59c2305b1f628e87f1c5d;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index e1942748d..1fcafc83f 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -110,10 +110,12 @@ Fields:
   is ignored or skipped, depending on context.
 * **ALL** when set, all branch conditional tests must pass in order for
   the branch to succeed.
-* **VLI** In VLSET mode, VL is set equal (truncated) to the first
-  branch which succeeds.  If VLI (Vector Length Inclusive) is clear,
+* **VLI** Identical to Data-dependent Fail-First mode.
+  In VLSET mode, VL is set equal (truncated) to the first point
+  where, assuming Conditions are tested sequentially, the  branch succeeds
+  *or fails*.  If VLI (Vector Length Inclusive) is clear,
   VL is truncated to *exclude* the current element, otherwise it is
-  included. SVSTATE.MVL is not changed.
+  included. SVSTATE.MVL is not changed: only VL.
 * **LRu**: Link Register Update. When set, Link Register will
   only be updated if the Branch Condition succeeds. This avoids
   destruction of LR during loops.
@@ -134,6 +136,9 @@ and `svstep` mode it is actually useful to use Branch Conditional even
 to perform no actual branch operation, i.e to point to the instruction
 after the branch.
 
+`VLSET` mode with Vertical-First is particularly unusual. TODO
+investigate svstep index checks.
+
 In particular, svstep mode is still useful for Horizontal-First Mode
 particularly in combination with REMAP. All "loop end" conditions
 will be tested on a per-element basis and placed into a Vector of CRs