From: lkcl <lkcl@web>
Date: Sun, 17 Apr 2022 10:35:07 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2761
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e12efef3878ed3336eb998aeeaf3406c12c979af;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 5488cbdaf..4a45b1db0 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -935,3 +935,14 @@ utilising internal Micro-coding and other techniques to transparently
 insert MV operations
 if necessary or desired, to give the level of efficiency or performance
 required.*
+
+# Twin (implicit) result operations
+
+Some operations in the Power ISA already target two 64-bit scalar
+registers: `lq` for example. Some mathematical algorithms are more
+efficient when there are two outputs rather than one.  64-bit multiply
+for example produces a 128 bit result
+
+* [[isa/svfixedarith]]
+* [[isa/svfparith]]
+