From: Giacomo Travaglini Date: Wed, 25 Sep 2019 12:11:22 +0000 (+0100) Subject: configs: Add simpleSystem helper to generate devices.SimpleSystem X-Git-Tag: v19.0.0.0~446 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e1488cd05c5a2446f9e31f53176b661e4f1d94a8;p=gem5.git configs: Add simpleSystem helper to generate devices.SimpleSystem This patch will make it possible to generate a SimpleSystem inheriting from a configurable base class. More practically it will be possible to inherit from a baremetal System (ArmSystem) rather than from a LinuxArmSystem Change-Id: I11553ae8045519059e159c555c6c9141bb4519b7 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21603 Maintainer: Andreas Sandberg Tested-by: kokoro --- diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py index 4d746edef..b73e7ae1f 100644 --- a/configs/example/arm/devices.py +++ b/configs/example/arm/devices.py @@ -186,106 +186,118 @@ class KvmCluster(CpuCluster): pass -class SimpleSystem(LinuxArmSystem): - cache_line_size = 64 - - def __init__(self, caches, mem_size, platform=None, **kwargs): - super(SimpleSystem, self).__init__(**kwargs) - - self.voltage_domain = VoltageDomain(voltage="1.0V") - self.clk_domain = SrcClockDomain(clock="1GHz", - voltage_domain=Parent.voltage_domain) - - if platform is None: - self.realview = VExpress_GEM5_V1() - else: - self.realview = platform - - if hasattr(self.realview.gic, 'cpu_addr'): - self.gic_cpu_addr = self.realview.gic.cpu_addr - self.flags_addr = self.realview.realview_io.pio_addr + 0x30 - - self.membus = MemBus() - - self.intrctrl = IntrControl() - self.terminal = Terminal() - self.vncserver = VncServer() - - self.iobus = IOXBar() - # CPUs->PIO - self.iobridge = Bridge(delay='50ns') - # Device DMA -> MEM - mem_range = self.realview._mem_regions[0] - assert long(mem_range.size()) >= long(Addr(mem_size)) - self.mem_ranges = [ AddrRange(start=mem_range.start, size=mem_size) ] - self._caches = caches - if self._caches: - self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]]) - else: - self.dmabridge = Bridge(delay='50ns', - ranges=[self.mem_ranges[0]]) - - self._pci_devices = 0 - self._clusters = [] - self._num_cpus = 0 - - def attach_pci(self, dev): - dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0) - self._pci_devices += 1 - self.realview.attachPciDevice(dev, self.iobus) - - def connect(self): - self.iobridge.master = self.iobus.slave - self.iobridge.slave = self.membus.master - - if self._caches: - self.iocache.mem_side = self.membus.slave - self.iocache.cpu_side = self.iobus.master - else: - self.dmabridge.master = self.membus.slave - self.dmabridge.slave = self.iobus.master - - if hasattr(self.realview.gic, 'cpu_addr'): - self.gic_cpu_addr = self.realview.gic.cpu_addr - self.realview.attachOnChipIO(self.membus, self.iobridge) - self.realview.attachIO(self.iobus) - self.system_port = self.membus.slave - - def numCpuClusters(self): - return len(self._clusters) - - def addCpuCluster(self, cpu_cluster, num_cpus): - assert cpu_cluster not in self._clusters - assert num_cpus > 0 - self._clusters.append(cpu_cluster) - self._num_cpus += num_cpus - - def numCpus(self): - return self._num_cpus +def simpleSystem(BaseSystem, caches, mem_size, platform=None, **kwargs): + """ + Create a simple system example. The base class in configurable so + that it is possible (e.g) to link the platform (hardware configuration) + with a baremetal ArmSystem or with a LinuxArmSystem. + """ + class SimpleSystem(BaseSystem): + cache_line_size = 64 + + def __init__(self, caches, mem_size, platform=None, **kwargs): + super(SimpleSystem, self).__init__(**kwargs) + + self.voltage_domain = VoltageDomain(voltage="1.0V") + self.clk_domain = SrcClockDomain( + clock="1GHz", + voltage_domain=Parent.voltage_domain) + + if platform is None: + self.realview = VExpress_GEM5_V1() + else: + self.realview = platform + + if hasattr(self.realview.gic, 'cpu_addr'): + self.gic_cpu_addr = self.realview.gic.cpu_addr + self.flags_addr = self.realview.realview_io.pio_addr + 0x30 + + self.membus = MemBus() + + self.intrctrl = IntrControl() + self.terminal = Terminal() + self.vncserver = VncServer() + + self.iobus = IOXBar() + # CPUs->PIO + self.iobridge = Bridge(delay='50ns') + # Device DMA -> MEM + mem_range = self.realview._mem_regions[0] + assert long(mem_range.size()) >= long(Addr(mem_size)) + self.mem_ranges = [ + AddrRange(start=mem_range.start, size=mem_size) ] + + self._caches = caches + if self._caches: + self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]]) + else: + self.dmabridge = Bridge(delay='50ns', + ranges=[self.mem_ranges[0]]) + + self._pci_devices = 0 + self._clusters = [] + self._num_cpus = 0 + + def attach_pci(self, dev): + dev.pci_bus, dev.pci_dev, dev.pci_func = \ + (0, self._pci_devices + 1, 0) + self._pci_devices += 1 + self.realview.attachPciDevice(dev, self.iobus) + + def connect(self): + self.iobridge.master = self.iobus.slave + self.iobridge.slave = self.membus.master + + if self._caches: + self.iocache.mem_side = self.membus.slave + self.iocache.cpu_side = self.iobus.master + else: + self.dmabridge.master = self.membus.slave + self.dmabridge.slave = self.iobus.master + + if hasattr(self.realview.gic, 'cpu_addr'): + self.gic_cpu_addr = self.realview.gic.cpu_addr + self.realview.attachOnChipIO(self.membus, self.iobridge) + self.realview.attachIO(self.iobus) + self.system_port = self.membus.slave + + def numCpuClusters(self): + return len(self._clusters) + + def addCpuCluster(self, cpu_cluster, num_cpus): + assert cpu_cluster not in self._clusters + assert num_cpus > 0 + self._clusters.append(cpu_cluster) + self._num_cpus += num_cpus + + def numCpus(self): + return self._num_cpus + + def addCaches(self, need_caches, last_cache_level): + if not need_caches: + # connect each cluster to the memory hierarchy + for cluster in self._clusters: + cluster.connectMemSide(self.membus) + return + + cluster_mem_bus = self.membus + assert last_cache_level >= 1 and last_cache_level <= 3 + for cluster in self._clusters: + cluster.addL1() + if last_cache_level > 1: + for cluster in self._clusters: + cluster.addL2(cluster.clk_domain) + if last_cache_level > 2: + max_clock_cluster = max(self._clusters, + key=lambda c: c.clk_domain.clock[0]) + self.l3 = L3(clk_domain=max_clock_cluster.clk_domain) + self.toL3Bus = L2XBar(width=64) + self.toL3Bus.master = self.l3.cpu_side + self.l3.mem_side = self.membus.slave + cluster_mem_bus = self.toL3Bus - def addCaches(self, need_caches, last_cache_level): - if not need_caches: # connect each cluster to the memory hierarchy for cluster in self._clusters: - cluster.connectMemSide(self.membus) - return + cluster.connectMemSide(cluster_mem_bus) - cluster_mem_bus = self.membus - assert last_cache_level >= 1 and last_cache_level <= 3 - for cluster in self._clusters: - cluster.addL1() - if last_cache_level > 1: - for cluster in self._clusters: - cluster.addL2(cluster.clk_domain) - if last_cache_level > 2: - max_clock_cluster = max(self._clusters, - key=lambda c: c.clk_domain.clock[0]) - self.l3 = L3(clk_domain=max_clock_cluster.clk_domain) - self.toL3Bus = L2XBar(width=64) - self.toL3Bus.master = self.l3.cpu_side - self.l3.mem_side = self.membus.slave - cluster_mem_bus = self.toL3Bus - - # connect each cluster to the memory hierarchy - for cluster in self._clusters: - cluster.connectMemSide(cluster_mem_bus) + return SimpleSystem(caches, mem_size, platform, **kwargs) diff --git a/configs/example/arm/fs_bigLITTLE.py b/configs/example/arm/fs_bigLITTLE.py index 1407705b6..75567e145 100644 --- a/configs/example/arm/fs_bigLITTLE.py +++ b/configs/example/arm/fs_bigLITTLE.py @@ -119,7 +119,8 @@ def createSystem(caches, kernel, bootscript, platform = ObjectList.platform_list.get(machine_type) m5.util.inform("Simulated platform: %s", platform.__name__) - sys = devices.SimpleSystem(caches, default_mem_size, platform(), + sys = devices.simpleSystem(LinuxArmSystem, + caches, default_mem_size, platform(), kernel=SysPaths.binary(kernel), readfile=bootscript) diff --git a/configs/example/arm/starter_fs.py b/configs/example/arm/starter_fs.py index 4061501ba..36c51d675 100644 --- a/configs/example/arm/starter_fs.py +++ b/configs/example/arm/starter_fs.py @@ -104,7 +104,8 @@ def create(args): # Only simulate caches when using a timing CPU (e.g., the HPI model) want_caches = True if mem_mode == "timing" else False - system = devices.SimpleSystem(want_caches, + system = devices.simpleSystem(LinuxArmSystem, + want_caches, args.mem_size, mem_mode=mem_mode, kernel=SysPaths.binary(args.kernel),