From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 17 Mar 2014 13:41:41 +0000 (+0100)
Subject: Fixed typo in RTLIL::Module::addAdff()
X-Git-Tag: yosys-0.3.0~38
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e164edc8d11356c0999c44dfdb52d0b2b337f212;p=yosys.git

Fixed typo in RTLIL::Module::addAdff()
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 2b28f3232..1d53bc79b 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1096,7 +1096,7 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk
 {
 	RTLIL::Cell *cell = new RTLIL::Cell;
 	cell->name = name;
-	cell->type = "$dffsr";
+	cell->type = "$adff";
 	cell->parameters["\\CLK_POLARITY"] = clk_polarity;
 	cell->parameters["\\ARST_POLARITY"] = arst_polarity;
 	cell->parameters["\\ARST_VALUE"] = arst_value;