From: Gabriel L. Somlo <gsomlo@gmail.com>
Date: Wed, 17 Apr 2019 14:39:35 +0000 (-0400)
Subject: build/sim/core: Initialize Verilator commandArgs
X-Git-Tag: 24jan2021_ls180~1327^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e1683078ece9914c4619879a5fdef46300ac64a4;p=litex.git

build/sim/core: Initialize Verilator commandArgs

Required when DUT is using plusargs. Prevents Verilator simulation
from crashing with "Verilog called $test$plusargs or $value$plusargs
without testbench C first calling Verilated::commandArgs(argc,argv)".
---

diff --git a/litex/build/sim/core/sim.c b/litex/build/sim/core/sim.c
index 32124ee1..3f7ad648 100644
--- a/litex/build/sim/core/sim.c
+++ b/litex/build/sim/core/sim.c
@@ -203,7 +203,7 @@ static void cb(int sock, short which, void *arg)
   }
 }
 
-int main()
+int main(int argc, char *argv[])
 {
   void *vdut=NULL;
   struct timeval tv;
@@ -224,6 +224,7 @@ int main()
     goto out;
   }
 
+  litex_sim_init_cmdargs(argc, argv);
   if(RC_OK != (ret = litex_sim_initialize_all(&vdut, base)))
   {
     goto out;
diff --git a/litex/build/sim/core/veril.cpp b/litex/build/sim/core/veril.cpp
index ef43fb1d..6821e207 100644
--- a/litex/build/sim/core/veril.cpp
+++ b/litex/build/sim/core/veril.cpp
@@ -17,6 +17,11 @@ extern "C" void litex_sim_eval(void *vdut)
   dut->eval();
 }
 
+extern "C" void litex_sim_init_cmdargs(int argc, char *argv[])
+{
+  Verilated::commandArgs(argc, argv);
+}
+
 extern "C" void litex_sim_init_tracer(void *vdut)
 {
   Vdut *dut = (Vdut*)vdut;
diff --git a/litex/build/sim/core/veril.h b/litex/build/sim/core/veril.h
index 35326ade..b8c5f165 100644
--- a/litex/build/sim/core/veril.h
+++ b/litex/build/sim/core/veril.h
@@ -4,6 +4,7 @@
 #define __VERIL_H_
 
 #ifdef __cplusplus
+extern "C" void litex_sim_init_cmdargs(int argc, char *argv[]);
 extern "C" void litex_sim_eval(void *vdut);
 extern "C" void litex_sim_init_tracer(void *vdut);
 extern "C" void litex_sim_tracer_dump();