From: lkcl Date: Tue, 25 Apr 2023 07:49:38 +0000 (+0100) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e18922e5b0b710d9f52dde7779a946c74c4d7da0;p=libreriscv.git --- diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index 408cbf641..0080ee163 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -77,8 +77,8 @@ Note that in immediate setting mode VL and MVL start from **one** but that this is compensated for in the assembly notation. i.e. that an immediate value of 1 in assembler notation actually places the value 0b0000000 in the `SVi` field bits: on execution the `setvl` instruction adds one to -the decoded `SVi` field bits, resulting in VL/MVL being set to 1. This -allows VL to be set to values ranging from 1 to 128 with only 7 bits +the decoded `SVi` field bits, resulting in VL/MVL being set to 1. In future +this will allow VL to be set to values ranging from 1 to 128 with only 7 bits instead of 8. Setting VL/MVL to 0 would result in all Vector operations becoming `nop`. If this is truly desired (nop behaviour) then setting VL and MVL to zero is to be done via the [[SVSTATE SPR|sv/sprs]].