From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 27 Jan 2020 22:02:13 +0000 (-0800)
Subject: Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
X-Git-Tag: working-ls180~843^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8;p=yosys.git

Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards

Just like Verilog...
---

diff --git a/passes/pmgen/ice40_wrapcarry.cc b/passes/pmgen/ice40_wrapcarry.cc
index d458dce46..0053c8872 100644
--- a/passes/pmgen/ice40_wrapcarry.cc
+++ b/passes/pmgen/ice40_wrapcarry.cc
@@ -127,7 +127,7 @@ struct Ice40WrapCarryPass : public Pass {
 					lut->setParam(ID(WIDTH), 4);
 					lut->setParam(ID(LUT), cell->getParam(ID(LUT)));
 					auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3));
-					lut->setPort(ID(A), {cell->getPort(ID(I0)), cell->getPort(ID(A)), cell->getPort(ID(B)), I3 });
+					lut->setPort(ID(A), { I3, cell->getPort(ID(B)), cell->getPort(ID(A)), cell->getPort(ID(I0)) });
 					lut->setPort(ID(Y), cell->getPort(ID(O)));
 
 					Const src;
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 940a11063..925ab31bb 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -140,7 +140,7 @@ static void run_ice40_opts(Module *module)
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "$lut";
 				auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)));
-				cell->setPort("\\A", { get_bit_or_zero(cell->getPort("\\I0")), inbit[0], inbit[1], I3 });
+				cell->setPort("\\A", { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) });
 				cell->setPort("\\Y", cell->getPort("\\O"));
 				cell->unsetPort("\\B");
 				cell->unsetPort("\\CI");