From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Apr 2020 18:41:34 +0000 (+0100)
Subject: add memory get/set
X-Git-Tag: div_pipeline~1526
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e196b86c567587a82de24e43df9e324a81ecd26f;p=soc.git

add memory get/set
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index cc78a3f9..89917d9c 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -4,7 +4,13 @@ class ISACaller:
     def __init__(self):
         self.gpr = {} # TODO
         self.mem = {} # TODO
-        self.namespace = {'GPR': self.gpr, 'MEM': self.mem}
+        self.namespace = {'GPR': self.gpr,
+                          'MEM': self.mem,
+                          'memassign': self.memassign
+                         }
+
+    def memassign(self, ea, sz, val):
+        pass
 
 def inject(context):
     """ Decorator factory. """
diff --git a/src/soc/decoder/power_pseudo.py b/src/soc/decoder/power_pseudo.py
index 9ed82951..c4f962a2 100644
--- a/src/soc/decoder/power_pseudo.py
+++ b/src/soc/decoder/power_pseudo.py
@@ -117,10 +117,20 @@ RT <- (load_data[56:63] || load_data[48:55]
 testgpr = """
 GPR(5) <- x
 """
+testmem = """
+a <- (RA|0)
+b <- (RB|0)
+RA <- MEM(RB, 2)
+EA <- a + 1
+MEM(EA, 1) <- (RS)[56:63]
+RB <- RA
+RA <- EA
+"""
 #code = testmul
 #code = testgetzero
 #code = testcat
-code = testgpr
+#code = testgpr
+code = testmem
 #code = testreg
 #code = cnttzd
 #code = cmpi
@@ -140,6 +150,26 @@ def tolist(num):
 def get_reg_hex(reg):
     return hex(reg.value)
 
+class Mem:
+
+    def __init__(self):
+        self.mem = []
+        for i in range(128):
+            self.mem.append(i)
+
+    def __call__(self, addr, sz):
+        res = []
+        for s in range(sz): # TODO: big/little-end
+            res.append(SelectableInt(self.mem[addr.value + s], 8))
+        print ("memread", addr, sz, res)
+        return selectconcat(*res)
+
+    def memassign(self, addr, sz, val):
+        print ("memassign", addr, sz, val)
+        for s in range(sz):
+            byte = (val.value) >> (s*8) & 0xff # TODO: big/little-end
+            self.mem[addr.value + s] = byte
+
 
 class GPR(dict):
     def __init__(self, sd, regfile):
@@ -185,11 +215,11 @@ def test():
 
     gsc = GardenSnakeCompiler()
 
-    # XXX unused!  see GPR instead
     gsc.regfile = {}
     for i in range(32):
         gsc.regfile[i] = i
     gsc.gpr = GPR(gsc.parser.sd, gsc.regfile)
+    gsc.mem = Mem()
 
     _compile = gsc.compile
 
@@ -219,6 +249,8 @@ def test():
     d["SelectableInt"] = SelectableInt
     d["concat"] = selectconcat
     d["GPR"] = gsc.gpr
+    d["MEM"] = gsc.mem
+    d["memassign"] = gsc.mem.memassign
 
     form = 'X'
     gsc.gpr.set_form(form)
@@ -269,7 +301,9 @@ def test():
             print(decode.sigforms['X'])
             x = yield decode.sigforms['X'].RS
             ra = yield decode.sigforms['X'].RA
+            rb = yield decode.sigforms['X'].RB
             print("RA", ra, d['RA'])
+            print("RB", rb, d['RB'])
             print("RS", x)
 
             for wname in gsc.parser.write_regs:
@@ -286,6 +320,12 @@ def test():
     for i in range(len(gsc.gpr)):
         print("regfile", i, get_reg_hex(gsc.gpr[i]))
 
+    for i in range(0, len(gsc.mem.mem), 16):
+        hexstr = []
+        for j in range(16):
+            hexstr.append("%02x" % gsc.mem.mem[i+j])
+        hexstr = ' '.join(hexstr)
+        print ("mem %4x" % i, hexstr)
 
 if __name__ == '__main__':
     test()
diff --git a/src/soc/decoder/pseudo/parser.py b/src/soc/decoder/pseudo/parser.py
index 437310ef..9384ca21 100644
--- a/src/soc/decoder/pseudo/parser.py
+++ b/src/soc/decoder/pseudo/parser.py
@@ -318,6 +318,15 @@ class PowerParser:
                 # replace GPR(x) with GPR[x]
                 idx = p[1].args[0]
                 p[1] = ast.Subscript(p[1].func, idx)
+            elif isinstance(p[1], ast.Call) and p[1].func.id == 'MEM':
+                print ("mem assign")
+                print(astor.dump_tree(p[1]))
+                p[1].func.id = "memassign" # change function name to set
+                p[1].args.append(p[3])
+                p[0] = p[1]
+                print ("mem rewrite")
+                print(astor.dump_tree(p[0]))
+                return
             else:
                 print ("help, help")
                 print(astor.dump_tree(p[1]))
diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index 36948940..d26074cf 100644
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -80,7 +80,8 @@ class PyISAWriter(ISA):
 
 if __name__ == '__main__':
     isa = PyISAWriter()
-    isa.write_pysource('fixedload')
+    isa.write_pysource('fixedstore')
     exit(0)
+    isa.write_pysource('fixedload')
     isa.write_pysource('comparefixed')
     isa.write_pysource('fixedarith')