From: pham.michael.98@a029fe8ac2da19fcd7269c492cf0410b2e5fd4cc <phammichael98@web>
Date: Sat, 14 Sep 2019 21:01:40 +0000 (+0100)
Subject: Add verilog implementation of displayport
X-Git-Tag: convert-csv-opcode-to-binary~4061
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e1a02941acb8487055f9867d83664a6b1361ddc3;p=libreriscv.git

Add verilog implementation of displayport
---

diff --git a/shakti/displayport.mdwn b/shakti/displayport.mdwn
index 569518a2a..948a941fb 100644
--- a/shakti/displayport.mdwn
+++ b/shakti/displayport.mdwn
@@ -1,3 +1,5 @@
 # DisplayPort
 
-<https://github.com/hamsternz/FPGA_DisplayPort>
+Verilog version: <https://github.com/hamsternz/DisplayPort_Verilog>
+
+VHDL version: <https://github.com/hamsternz/FPGA_DisplayPort>