From: Chun-Chen TK Hsu Date: Tue, 8 Oct 2019 11:02:33 +0000 (+0800) Subject: system-arm: Initialize ICC_SRE_EL3 register of all CPUs X-Git-Tag: v19.0.0.0~465 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e1a97946510dd5551f2adf4d7367a954cb34330b;p=gem5.git system-arm: Initialize ICC_SRE_EL3 register of all CPUs Fix a bug that only CPU0 initialized ICC_SRE_EL3 register. Change-Id: I625c9a25bada80b864e5eb5a8b8be14ee324b801 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21539 Tested-by: kokoro Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini --- diff --git a/system/arm/aarch64_bootloader/boot.S b/system/arm/aarch64_bootloader/boot.S index 5e5e39439..38090c8f2 100644 --- a/system/arm/aarch64_bootloader/boot.S +++ b/system/arm/aarch64_bootloader/boot.S @@ -91,12 +91,12 @@ _start: str w0, [x1], #4 /* SRE & Disable IRQ/FIQ Bypass & Allow EL2 access to ICC_SRE_EL2 */ - mrs x10, S3_6_C12_C12_5 // read ICC_SRE_EL3 +2: mrs x10, S3_6_C12_C12_5 // read ICC_SRE_EL3 orr x10, x10, #0xf // enable 0xf msr S3_6_C12_C12_5, x10 // write ICC_SRE_EL3 isb -2: mov x0, #1 + mov x0, #1 msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable msr S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable #else