From: Luke Kenneth Casson Leighton Date: Tue, 11 Aug 2020 14:08:20 +0000 (+0000) Subject: test_issuer.il with an alternative read/write port bus structure X-Git-Tag: partial-core-ls180-gdsii~88 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e1c0e8550af2c5a97bd8298af0b4b3be4d7da0ea;p=soclayout.git test_issuer.il with an alternative read/write port bus structure brings gate count down quite a lot --- diff --git a/experiments9/non_generated/test_issuer.il b/experiments9/non_generated/test_issuer.il index 6cbad27..764a234 100644 --- a/experiments9/non_generated/test_issuer.il +++ b/experiments9/non_generated/test_issuer.il @@ -138368,17 +138368,17 @@ module \int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 output 2 \dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 input 3 \src1__ren + wire width 64 output 3 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 4 \src1__data_o + wire width 32 input 4 \src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 input 5 \src3__ren + wire width 64 output 5 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 6 \src3__data_o + wire width 32 input 6 \src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 input 7 \wen + wire width 64 input 7 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 8 \data_i + wire width 32 input 8 \wen attribute \src "simple/issuer.py:89" wire width 1 input 9 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" @@ -144700,29 +144700,29 @@ module \cr attribute \src "simple/issuer.py:89" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 1 \full_rd__ren + wire width 32 output 1 \full_rd__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 output 2 \full_rd__data_o + wire width 8 input 2 \full_rd__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 3 \src1__ren + wire width 4 output 3 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 4 \src1__data_o + wire width 8 input 4 \src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 5 \src2__ren + wire width 4 output 5 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 6 \src2__data_o + wire width 8 input 6 \src2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 7 \src3__ren + wire width 4 output 7 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 8 \src3__data_o + wire width 8 input 8 \src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 9 \full_wr__wen + wire width 32 input 9 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 input 10 \full_wr__data_i + wire width 8 input 10 \full_wr__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 11 \wen + wire width 4 input 11 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 12 \data_i + wire width 8 input 12 \wen attribute \src "simple/issuer.py:89" wire width 1 input 13 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" @@ -147207,29 +147207,29 @@ module \xer attribute \src "simple/issuer.py:89" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 1 \src1__ren + wire width 2 output 1 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 2 \src1__data_o + wire width 3 input 2 \src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 3 \src2__ren + wire width 2 output 3 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 4 \src2__data_o + wire width 3 input 4 \src2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 5 \src3__ren + wire width 2 output 5 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 6 \src3__data_o + wire width 3 input 6 \src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 7 \wen + wire width 2 input 7 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 8 \data_i + wire width 3 input 8 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 9 \wen$1 + wire width 2 input 9 \data_i$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 10 \data_i$2 + wire width 3 input 10 \wen$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 11 \wen$3 + wire width 2 input 11 \data_i$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 12 \data_i$4 + wire width 3 input 12 \wen$4 attribute \src "simple/issuer.py:89" wire width 1 input 13 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" @@ -147506,22 +147506,22 @@ module \xer assign \reg_0_dest10__wen 1'0 assign \reg_1_dest11__wen 1'0 assign \reg_2_dest12__wen 1'0 - assign { \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen$3 + assign { \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen$4 sync init end process $group_15 assign \reg_0_dest10__data_i 2'00 - assign \reg_0_dest10__data_i \data_i$4 + assign \reg_0_dest10__data_i \data_i$3 sync init end process $group_16 assign \reg_1_dest11__data_i 2'00 - assign \reg_1_dest11__data_i \data_i$4 + assign \reg_1_dest11__data_i \data_i$3 sync init end process $group_17 assign \reg_2_dest12__data_i 2'00 - assign \reg_2_dest12__data_i \data_i$4 + assign \reg_2_dest12__data_i \data_i$3 sync init end process $group_18 @@ -147550,22 +147550,22 @@ module \xer assign \reg_0_dest30__wen 1'0 assign \reg_1_dest31__wen 1'0 assign \reg_2_dest32__wen 1'0 - assign { \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$1 + assign { \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$2 sync init end process $group_27 assign \reg_0_dest30__data_i 2'00 - assign \reg_0_dest30__data_i \data_i$2 + assign \reg_0_dest30__data_i \data_i$1 sync init end process $group_28 assign \reg_1_dest31__data_i 2'00 - assign \reg_1_dest31__data_i \data_i$2 + assign \reg_1_dest31__data_i \data_i$1 sync init end process $group_29 assign \reg_2_dest32__data_i 2'00 - assign \reg_2_dest32__data_i \data_i$2 + assign \reg_2_dest32__data_i \data_i$1 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" @@ -148202,13 +148202,13 @@ module \fast attribute \src "simple/issuer.py:89" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 1 \src1__ren + wire width 64 output 1 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 2 \src1__data_o + wire width 5 input 2 \src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 3 \wen + wire width 64 input 3 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 4 \data_i + wire width 5 input 4 \wen attribute \src "simple/issuer.py:89" wire width 1 input 5 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" @@ -148954,9 +148954,9 @@ module \state attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 8 \data_i$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \wen$2 + wire width 64 input 9 \data_i$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 10 \data_i$3 + wire width 2 input 10 \wen$3 attribute \src "simple/issuer.py:89" wire width 1 input 11 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" @@ -149094,17 +149094,17 @@ module \state process $group_10 assign \reg_0_msr0__wen 1'0 assign \reg_1_msr1__wen 1'0 - assign { \reg_1_msr1__wen \reg_0_msr0__wen } \wen$2 + assign { \reg_1_msr1__wen \reg_0_msr0__wen } \wen$3 sync init end process $group_12 assign \reg_0_msr0__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_0_msr0__data_i \data_i$3 + assign \reg_0_msr0__data_i \data_i$2 sync init end process $group_13 assign \reg_1_msr1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_1_msr1__data_i \data_i$3 + assign \reg_1_msr1__data_i \data_i$2 sync init end process $group_14 @@ -154141,131 +154141,131 @@ module \core connect \dbus__dat_w \dbus__dat_w end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \int_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \int_src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \int_src3__ren + wire width 32 \int_src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \int_src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \int_wen + wire width 32 \int_src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \int_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \int_wen cell \int \int connect \coresync_clk \coresync_clk connect \dmi__ren \dmi__ren connect \dmi__data_o \dmi__data_o - connect \src1__ren \int_src1__ren connect \src1__data_o \int_src1__data_o - connect \src3__ren \int_src3__ren + connect \src1__ren \int_src1__ren connect \src3__data_o \int_src3__data_o - connect \wen \int_wen + connect \src3__ren \int_src3__ren connect \data_i \int_data_i + connect \wen \int_wen connect \coresync_rst \coresync_rst end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_full_rd__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 32 \cr_full_rd__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_src1__ren + wire width 8 \cr_full_rd__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \cr_src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_src2__ren + wire width 8 \cr_src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \cr_src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_src3__ren + wire width 8 \cr_src2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \cr_src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_full_wr__wen + wire width 8 \cr_src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 32 \cr_full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_wen + wire width 8 \cr_full_wr__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \cr_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_wen cell \cr \cr connect \coresync_clk \coresync_clk - connect \full_rd__ren \cr_full_rd__ren connect \full_rd__data_o \cr_full_rd__data_o - connect \src1__ren \cr_src1__ren + connect \full_rd__ren \cr_full_rd__ren connect \src1__data_o \cr_src1__data_o - connect \src2__ren \cr_src2__ren + connect \src1__ren \cr_src1__ren connect \src2__data_o \cr_src2__data_o - connect \src3__ren \cr_src3__ren + connect \src2__ren \cr_src2__ren connect \src3__data_o \cr_src3__data_o - connect \full_wr__wen \cr_full_wr__wen + connect \src3__ren \cr_src3__ren connect \full_wr__data_i \cr_full_wr__data_i - connect \wen \cr_wen + connect \full_wr__wen \cr_full_wr__wen connect \data_i \cr_data_i + connect \wen \cr_wen connect \coresync_rst \coresync_rst end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 \xer_src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src2__ren + wire width 3 \xer_src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 \xer_src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src3__ren + wire width 3 \xer_src2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 \xer_src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen + wire width 3 \xer_src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 \xer_data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$153 + wire width 3 \xer_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_data_i$153 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$154 + wire width 3 \xer_wen$154 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$155 + wire width 2 \xer_data_i$155 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$156 + wire width 3 \xer_wen$156 cell \xer \xer connect \coresync_clk \coresync_clk - connect \src1__ren \xer_src1__ren connect \src1__data_o \xer_src1__data_o - connect \src2__ren \xer_src2__ren + connect \src1__ren \xer_src1__ren connect \src2__data_o \xer_src2__data_o - connect \src3__ren \xer_src3__ren + connect \src2__ren \xer_src2__ren connect \src3__data_o \xer_src3__data_o - connect \wen \xer_wen + connect \src3__ren \xer_src3__ren connect \data_i \xer_data_i - connect \wen$1 \xer_wen$153 - connect \data_i$2 \xer_data_i$154 - connect \wen$3 \xer_wen$155 - connect \data_i$4 \xer_data_i$156 + connect \wen \xer_wen + connect \data_i$1 \xer_data_i$153 + connect \wen$2 \xer_wen$154 + connect \data_i$3 \xer_data_i$155 + connect \wen$4 \xer_wen$156 connect \coresync_rst \coresync_rst end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \fast_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \fast_src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \fast_wen + wire width 5 \fast_src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \fast_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \fast_wen cell \fast \fast connect \coresync_clk \coresync_clk - connect \src1__ren \fast_src1__ren connect \src1__data_o \fast_src1__data_o - connect \wen \fast_wen + connect \src1__ren \fast_src1__ren connect \data_i \fast_data_i + connect \wen \fast_wen connect \coresync_rst \coresync_rst end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \state_data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \state_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \state_data_i$157 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \state_wen cell \state \state connect \coresync_clk \coresync_clk connect \cia__ren \cia__ren @@ -154276,8 +154276,8 @@ module \core connect \wen \wen connect \data_i \data_i connect \data_i$1 \state_data_i - connect \wen$2 \state_wen - connect \data_i$3 \state_data_i$157 + connect \data_i$2 \state_data_i$157 + connect \wen$3 \state_wen connect \coresync_rst \coresync_rst end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" @@ -158736,11 +158736,11 @@ module \core assign \rdflag_INT_ra_0 \pdecode2_reg1_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" wire width 1 $257 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" cell $and $258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -158751,9 +158751,9 @@ module \core connect \B \fu_enable [0] connect \Y $257 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" wire width 1 $259 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" cell $and $260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -158769,21 +158769,21 @@ module \core assign \pick $259 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" wire width 1 \pick$261 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" wire width 1 \pick$262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" wire width 1 \pick$263 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" wire width 1 \pick$264 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" wire width 1 \pick$265 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" wire width 1 \pick$266 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" wire width 1 \pick$267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" wire width 1 \pick$268 process $group_160 assign \rdpick_INT_ra_i 9'000000000 @@ -158806,23 +158806,12 @@ module \core assign \fus_cu_rd__go_i [3] \rdpick_XER_xer_ca_o [0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $269 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [0] - connect \B \rdpick_INT_ra_en_o - connect \Y $269 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - wire width 32 $271 + wire width 32 $269 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - cell $sshl $272 + cell $sshl $270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -158830,77 +158819,106 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \pdecode2_reg1 - connect \Y $271 + connect \Y $269 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $273 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $272 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [1] + connect \A \rdpick_INT_ra_o [0] connect \B \rdpick_INT_ra_en_o - connect \Y $273 + connect \Y $272 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - wire width 32 $275 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - cell $sshl $276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $274 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $269 + connect \S $272 + connect \Y $271 + end + process $group_162 + assign \read_en 32'00000000000000000000000000000000 + assign \read_en $271 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $275 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_reg1 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [0] + connect \B \rdpick_INT_ra_en_o connect \Y $275 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + process $group_163 + assign \fus_src1_i 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $275 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + case 1'1 + assign \fus_src1_i \int_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" wire width 1 $277 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" cell $and $278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [2] - connect \B \rdpick_INT_ra_en_o + connect \A \fus_cu_rd__rel_o$30 [0] + connect \B \fu_enable [1] connect \Y $277 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - wire width 32 $279 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - cell $sshl $280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_reg1 - connect \Y $279 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $281 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [3] - connect \B \rdpick_INT_ra_en_o - connect \Y $281 + connect \A $277 + connect \B \rdflag_INT_ra_0 + connect \Y $279 + end + process $group_164 + assign \pick$261 1'0 + assign \pick$261 $279 + sync init + end + process $group_165 + assign \fus_cu_rd__go_i$31 6'000000 + assign \fus_cu_rd__go_i$31 [0] \rdpick_INT_ra_o [1] + assign \fus_cu_rd__go_i$31 [1] \rdpick_INT_rbc_o [1] + assign \fus_cu_rd__go_i$31 [2] \rdpick_CR_full_cr_o + assign \fus_cu_rd__go_i$31 [3] \rdpick_CR_cr_a_o [0] + assign \fus_cu_rd__go_i$31 [4] \rdpick_CR_cr_b_o + assign \fus_cu_rd__go_i$31 [5] \rdpick_CR_cr_c_o + sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$281 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - wire width 32 $283 + wire width 32 $282 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - cell $sshl $284 + cell $sshl $283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -158908,73 +158926,100 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \pdecode2_reg1 - connect \Y $283 + connect \Y $282 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" wire width 1 $285 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" cell $and $286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [4] + connect \A \rdpick_INT_ra_o [1] connect \B \rdpick_INT_ra_en_o connect \Y $285 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - wire width 32 $287 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - cell $sshl $288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_reg1 - connect \Y $287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $287 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $282 + connect \S $285 + connect \Y $284 + end + process $group_166 + assign \read_en$281 32'00000000000000000000000000000000 + assign \read_en$281 $284 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $289 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $288 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [5] + connect \A \rdpick_INT_ra_o [1] connect \B \rdpick_INT_ra_en_o - connect \Y $289 + connect \Y $288 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - wire width 32 $291 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - cell $sshl $292 + process $group_167 + assign \fus_src1_i$32 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $288 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + case 1'1 + assign \fus_src1_i$32 \int_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_reg1 - connect \Y $291 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$33 [0] + connect \B \fu_enable [3] + connect \Y $290 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $293 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $294 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $292 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [6] - connect \B \rdpick_INT_ra_en_o - connect \Y $293 + connect \A $290 + connect \B \rdflag_INT_ra_0 + connect \Y $292 + end + process $group_168 + assign \pick$262 1'0 + assign \pick$262 $292 + sync init + end + process $group_169 + assign \fus_cu_rd__go_i$34 4'0000 + assign \fus_cu_rd__go_i$34 [0] \rdpick_INT_ra_o [2] + assign \fus_cu_rd__go_i$34 [1] \rdpick_INT_rbc_o [2] + assign \fus_cu_rd__go_i$34 [2] \rdpick_FAST_fast1_o [1] + assign \fus_cu_rd__go_i$34 [3] \rdpick_FAST_fast1_o [4] + sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$294 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" wire width 32 $295 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" @@ -158988,306 +159033,141 @@ module \core connect \B \pdecode2_reg1 connect \Y $295 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $297 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $298 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $297 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $298 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [7] + connect \A \rdpick_INT_ra_o [2] connect \B \rdpick_INT_ra_en_o + connect \Y $298 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $300 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $295 + connect \S $298 connect \Y $297 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - wire width 32 $299 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - cell $sshl $300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_reg1 - connect \Y $299 + process $group_170 + assign \read_en$294 32'00000000000000000000000000000000 + assign \read_en$294 $297 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 $301 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" cell $and $302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [8] + connect \A \rdpick_INT_ra_o [2] connect \B \rdpick_INT_ra_en_o connect \Y $301 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - wire width 32 $303 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - cell $sshl $304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_reg1 - connect \Y $303 - end - process $group_162 - assign \int_src1__ren 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $269 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src1__ren $271 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $273 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src1__ren $275 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $277 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src1__ren $279 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $281 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src1__ren $283 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $285 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src1__ren $287 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $289 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src1__ren $291 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $293 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src1__ren $295 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $297 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src1__ren $299 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + process $group_171 + assign \fus_src1_i$35 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" switch { $301 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 - assign \int_src1__ren $303 + assign \fus_src1_i$35 \int_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $305 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [0] - connect \B \rdpick_INT_ra_en_o - connect \Y $305 - end - process $group_163 - assign \fus_src1_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $305 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fus_src1_i \int_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $307 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $303 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$30 [0] - connect \B \fu_enable [1] - connect \Y $307 + connect \A \fus_cu_rd__rel_o$36 [0] + connect \B \fu_enable [4] + connect \Y $303 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $309 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $307 + connect \A $303 connect \B \rdflag_INT_ra_0 - connect \Y $309 - end - process $group_164 - assign \pick$261 1'0 - assign \pick$261 $309 - sync init + connect \Y $305 end - process $group_165 - assign \fus_cu_rd__go_i$31 6'000000 - assign \fus_cu_rd__go_i$31 [0] \rdpick_INT_ra_o [1] - assign \fus_cu_rd__go_i$31 [1] \rdpick_INT_rbc_o [1] - assign \fus_cu_rd__go_i$31 [2] \rdpick_CR_full_cr_o - assign \fus_cu_rd__go_i$31 [3] \rdpick_CR_cr_a_o [0] - assign \fus_cu_rd__go_i$31 [4] \rdpick_CR_cr_b_o - assign \fus_cu_rd__go_i$31 [5] \rdpick_CR_cr_c_o + process $group_172 + assign \pick$263 1'0 + assign \pick$263 $305 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $311 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [1] - connect \B \rdpick_INT_ra_en_o - connect \Y $311 - end - process $group_166 - assign \fus_src1_i$32 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $311 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fus_src1_i$32 \int_src1__data_o - end + process $group_173 + assign \fus_cu_rd__go_i$37 2'00 + assign \fus_cu_rd__go_i$37 [0] \rdpick_INT_ra_o [3] + assign \fus_cu_rd__go_i$37 [1] \rdpick_INT_rbc_o [3] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $313 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$33 [0] - connect \B \fu_enable [3] - connect \Y $313 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $315 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" + wire width 32 $308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" + cell $sshl $309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $313 - connect \B \rdflag_INT_ra_0 - connect \Y $315 - end - process $group_167 - assign \pick$262 1'0 - assign \pick$262 $315 - sync init - end - process $group_168 - assign \fus_cu_rd__go_i$34 4'0000 - assign \fus_cu_rd__go_i$34 [0] \rdpick_INT_ra_o [2] - assign \fus_cu_rd__go_i$34 [1] \rdpick_INT_rbc_o [2] - assign \fus_cu_rd__go_i$34 [2] \rdpick_FAST_fast1_o [1] - assign \fus_cu_rd__go_i$34 [3] \rdpick_FAST_fast1_o [4] - sync init + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_reg1 + connect \Y $308 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $317 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [2] + connect \A \rdpick_INT_ra_o [3] connect \B \rdpick_INT_ra_en_o - connect \Y $317 - end - process $group_169 - assign \fus_src1_i$35 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $317 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fus_src1_i$35 \int_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $319 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$36 [0] - connect \B \fu_enable [4] - connect \Y $319 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $321 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $319 - connect \B \rdflag_INT_ra_0 - connect \Y $321 + connect \Y $311 end - process $group_170 - assign \pick$263 1'0 - assign \pick$263 $321 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $313 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $308 + connect \S $311 + connect \Y $310 end - process $group_171 - assign \fus_cu_rd__go_i$37 2'00 - assign \fus_cu_rd__go_i$37 [0] \rdpick_INT_ra_o [3] - assign \fus_cu_rd__go_i$37 [1] \rdpick_INT_rbc_o [3] + process $group_174 + assign \read_en$307 32'00000000000000000000000000000000 + assign \read_en$307 $310 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $323 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $314 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159295,22 +159175,22 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [3] connect \B \rdpick_INT_ra_en_o - connect \Y $323 + connect \Y $314 end - process $group_172 + process $group_175 assign \fus_src1_i$38 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $323 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $314 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src1_i$38 \int_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $325 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159318,27 +159198,27 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$39 [0] connect \B \fu_enable [5] - connect \Y $325 + connect \Y $316 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $327 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $328 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $325 + connect \A $316 connect \B \rdflag_INT_ra_0 - connect \Y $327 + connect \Y $318 end - process $group_173 + process $group_176 assign \pick$264 1'0 - assign \pick$264 $327 + assign \pick$264 $318 sync init end - process $group_174 + process $group_177 assign \fus_cu_rd__go_i$40 6'000000 assign \fus_cu_rd__go_i$40 [0] \rdpick_INT_ra_o [4] assign \fus_cu_rd__go_i$40 [3] \rdpick_XER_xer_so_o [1] @@ -159348,10 +159228,27 @@ module \core assign \fus_cu_rd__go_i$40 [1] \rdpick_SPR_spr1_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $329 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $330 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" + wire width 32 $321 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" + cell $sshl $322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_reg1 + connect \Y $321 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $323 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159359,22 +159256,48 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [4] connect \B \rdpick_INT_ra_en_o - connect \Y $329 + connect \Y $324 end - process $group_175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $326 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $321 + connect \S $324 + connect \Y $323 + end + process $group_178 + assign \read_en$320 32'00000000000000000000000000000000 + assign \read_en$320 $323 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [4] + connect \B \rdpick_INT_ra_en_o + connect \Y $327 + end + process $group_179 assign \fus_src1_i$41 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $329 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $327 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src1_i$41 \int_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $331 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $332 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $329 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159382,37 +159305,54 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$42 [0] connect \B \fu_enable [6] - connect \Y $331 + connect \Y $329 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $333 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $331 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $331 + connect \A $329 connect \B \rdflag_INT_ra_0 - connect \Y $333 + connect \Y $331 end - process $group_176 + process $group_180 assign \pick$265 1'0 - assign \pick$265 $333 + assign \pick$265 $331 sync init end - process $group_177 + process $group_181 assign \fus_cu_rd__go_i$43 3'000 assign \fus_cu_rd__go_i$43 [0] \rdpick_INT_ra_o [5] assign \fus_cu_rd__go_i$43 [1] \rdpick_INT_rbc_o [4] assign \fus_cu_rd__go_i$43 [2] \rdpick_XER_xer_so_o [2] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $335 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $336 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" + wire width 32 $334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" + cell $sshl $335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_reg1 + connect \Y $334 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $336 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $337 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159420,22 +159360,48 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [5] connect \B \rdpick_INT_ra_en_o - connect \Y $335 + connect \Y $337 end - process $group_178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $339 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $334 + connect \S $337 + connect \Y $336 + end + process $group_182 + assign \read_en$333 32'00000000000000000000000000000000 + assign \read_en$333 $336 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $340 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [5] + connect \B \rdpick_INT_ra_en_o + connect \Y $340 + end + process $group_183 assign \fus_src1_i$44 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $335 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $340 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src1_i$44 \int_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $337 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $338 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $342 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159443,37 +159409,54 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$45 [0] connect \B \fu_enable [7] - connect \Y $337 + connect \Y $342 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $339 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $340 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $344 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $337 + connect \A $342 connect \B \rdflag_INT_ra_0 - connect \Y $339 + connect \Y $344 end - process $group_179 + process $group_184 assign \pick$266 1'0 - assign \pick$266 $339 + assign \pick$266 $344 sync init end - process $group_180 + process $group_185 assign \fus_cu_rd__go_i$46 3'000 assign \fus_cu_rd__go_i$46 [0] \rdpick_INT_ra_o [6] assign \fus_cu_rd__go_i$46 [1] \rdpick_INT_rbc_o [5] assign \fus_cu_rd__go_i$46 [2] \rdpick_XER_xer_so_o [3] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $341 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $342 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$346 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" + wire width 32 $347 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" + cell $sshl $348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_reg1 + connect \Y $347 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $349 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $350 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159481,22 +159464,48 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [6] connect \B \rdpick_INT_ra_en_o - connect \Y $341 + connect \Y $350 end - process $group_181 - assign \fus_src1_i$47 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $341 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fus_src1_i$47 \int_src1__data_o - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $352 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $347 + connect \S $350 + connect \Y $349 + end + process $group_186 + assign \read_en$346 32'00000000000000000000000000000000 + assign \read_en$346 $349 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $343 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $344 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $353 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [6] + connect \B \rdpick_INT_ra_en_o + connect \Y $353 + end + process $group_187 + assign \fus_src1_i$47 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $353 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + case 1'1 + assign \fus_src1_i$47 \int_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $355 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159504,27 +159513,27 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$48 [0] connect \B \fu_enable [8] - connect \Y $343 + connect \Y $355 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $345 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $346 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $357 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $343 + connect \A $355 connect \B \rdflag_INT_ra_0 - connect \Y $345 + connect \Y $357 end - process $group_182 + process $group_188 assign \pick$267 1'0 - assign \pick$267 $345 + assign \pick$267 $357 sync init end - process $group_183 + process $group_189 assign \fus_cu_rd__go_i$49 4'0000 assign \fus_cu_rd__go_i$49 [0] \rdpick_INT_ra_o [7] assign \fus_cu_rd__go_i$49 [1] \rdpick_INT_rbc_o [6] @@ -159532,10 +159541,53 @@ module \core assign \fus_cu_rd__go_i$49 [3] \rdpick_XER_xer_ca_o [2] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $347 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $348 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$359 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" + wire width 32 $360 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" + cell $sshl $361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_reg1 + connect \Y $360 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $362 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [7] + connect \B \rdpick_INT_ra_en_o + connect \Y $363 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $365 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $360 + connect \S $363 + connect \Y $362 + end + process $group_190 + assign \read_en$359 32'00000000000000000000000000000000 + assign \read_en$359 $362 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159543,22 +159595,22 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [7] connect \B \rdpick_INT_ra_en_o - connect \Y $347 + connect \Y $366 end - process $group_184 + process $group_191 assign \fus_src1_i$50 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $347 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $366 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src1_i$50 \int_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $349 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $350 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $368 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159566,37 +159618,54 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$51 [0] connect \B \fu_enable [9] - connect \Y $349 + connect \Y $368 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $351 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $352 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $349 + connect \A $368 connect \B \rdflag_INT_ra_0 - connect \Y $351 + connect \Y $370 end - process $group_185 + process $group_192 assign \pick$268 1'0 - assign \pick$268 $351 + assign \pick$268 $370 sync init end - process $group_186 + process $group_193 assign \fus_cu_rd__go_i$52 3'000 assign \fus_cu_rd__go_i$52 [0] \rdpick_INT_ra_o [8] assign \fus_cu_rd__go_i$52 [1] \rdpick_INT_rbc_o [7] assign \fus_cu_rd__go_i$52 [2] \rdpick_INT_rbc_o [9] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $353 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $354 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$372 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" + wire width 32 $373 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" + cell $sshl $374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_reg1 + connect \Y $373 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $376 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159604,38 +159673,173 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [8] connect \B \rdpick_INT_ra_en_o - connect \Y $353 + connect \Y $376 end - process $group_187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $378 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $373 + connect \S $376 + connect \Y $375 + end + process $group_194 + assign \read_en$372 32'00000000000000000000000000000000 + assign \read_en$372 $375 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $379 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [8] + connect \B \rdpick_INT_ra_en_o + connect \Y $379 + end + process $group_195 assign \fus_src1_i$53 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $353 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $379 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src1_i$53 \int_src1__data_o end sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 32 $381 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \read_en + connect \B \read_en$281 + connect \Y $381 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 32 $383 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \read_en$294 + connect \B \read_en$307 + connect \Y $383 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 32 $385 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $381 + connect \B $383 + connect \Y $385 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 32 $387 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \read_en$320 + connect \B \read_en$333 + connect \Y $387 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 32 $389 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \read_en$359 + connect \B \read_en$372 + connect \Y $389 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 32 $391 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \read_en$346 + connect \B $389 + connect \Y $391 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 32 $393 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $387 + connect \B $391 + connect \Y $393 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 32 $395 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $385 + connect \B $393 + connect \Y $395 + end + process $group_196 + assign \int_src1__ren 32'00000000000000000000000000000000 + assign \int_src1__ren $395 + sync init + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" wire width 1 \rdflag_INT_rbc_0 - process $group_188 + process $group_197 assign \rdflag_INT_rbc_0 1'0 assign \rdflag_INT_rbc_0 \pdecode2_reg2_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" wire width 1 \rdflag_INT_rbc_1 - process $group_189 + process $group_198 assign \rdflag_INT_rbc_1 1'0 assign \rdflag_INT_rbc_1 \pdecode2_reg3_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$355 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $356 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $357 + wire width 1 \pick$397 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $398 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159643,75 +159847,64 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [1] connect \B \fu_enable [0] - connect \Y $356 + connect \Y $398 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $358 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $359 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $400 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $356 + connect \A $398 connect \B \rdflag_INT_rbc_0 - connect \Y $358 + connect \Y $400 end - process $group_190 - assign \pick$355 1'0 - assign \pick$355 $358 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$360 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$361 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$362 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$363 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$364 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$365 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$366 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$367 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$368 - process $group_191 - assign \rdpick_INT_rbc_i 10'0000000000 - assign \rdpick_INT_rbc_i [0] \pick$355 - assign \rdpick_INT_rbc_i [1] \pick$360 - assign \rdpick_INT_rbc_i [2] \pick$361 - assign \rdpick_INT_rbc_i [3] \pick$362 - assign \rdpick_INT_rbc_i [4] \pick$363 - assign \rdpick_INT_rbc_i [5] \pick$364 - assign \rdpick_INT_rbc_i [6] \pick$365 - assign \rdpick_INT_rbc_i [7] \pick$366 - assign \rdpick_INT_rbc_i [8] \pick$367 - assign \rdpick_INT_rbc_i [9] \pick$368 + process $group_199 + assign \pick$397 1'0 + assign \pick$397 $400 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $369 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [0] - connect \B \rdpick_INT_rbc_en_o - connect \Y $369 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$403 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$404 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$409 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$410 + process $group_200 + assign \rdpick_INT_rbc_i 10'0000000000 + assign \rdpick_INT_rbc_i [0] \pick$397 + assign \rdpick_INT_rbc_i [1] \pick$402 + assign \rdpick_INT_rbc_i [2] \pick$403 + assign \rdpick_INT_rbc_i [3] \pick$404 + assign \rdpick_INT_rbc_i [4] \pick$405 + assign \rdpick_INT_rbc_i [5] \pick$406 + assign \rdpick_INT_rbc_i [6] \pick$407 + assign \rdpick_INT_rbc_i [7] \pick$408 + assign \rdpick_INT_rbc_i [8] \pick$409 + assign \rdpick_INT_rbc_i [9] \pick$410 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$411 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - wire width 32 $371 + wire width 32 $412 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - cell $sshl $372 + cell $sshl $413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159719,51 +159912,96 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \pdecode2_reg2 - connect \Y $371 + connect \Y $412 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $373 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $374 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $414 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [1] + connect \A \rdpick_INT_rbc_o [0] connect \B \rdpick_INT_rbc_en_o - connect \Y $373 + connect \Y $415 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - wire width 32 $375 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - cell $sshl $376 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $417 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $412 + connect \S $415 + connect \Y $414 + end + process $group_201 + assign \read_en$411 32'00000000000000000000000000000000 + assign \read_en$411 $414 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $418 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_reg2 - connect \Y $375 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rbc_o [0] + connect \B \rdpick_INT_rbc_en_o + connect \Y $418 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $377 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $378 + process $group_202 + assign \fus_src2_i 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $418 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + case 1'1 + assign \fus_src2_i \int_src3__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $420 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [2] - connect \B \rdpick_INT_rbc_en_o - connect \Y $377 + connect \A \fus_cu_rd__rel_o$30 [1] + connect \B \fu_enable [1] + connect \Y $420 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $420 + connect \B \rdflag_INT_rbc_0 + connect \Y $422 + end + process $group_203 + assign \pick$402 1'0 + assign \pick$402 $422 + sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$424 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - wire width 32 $379 + wire width 32 $425 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - cell $sshl $380 + cell $sshl $426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159771,77 +160009,96 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \pdecode2_reg2 - connect \Y $379 + connect \Y $425 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $381 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $382 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $428 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [3] + connect \A \rdpick_INT_rbc_o [1] connect \B \rdpick_INT_rbc_en_o - connect \Y $381 + connect \Y $428 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - wire width 32 $383 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - cell $sshl $384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_reg2 - connect \Y $383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $430 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $425 + connect \S $428 + connect \Y $427 + end + process $group_204 + assign \read_en$424 32'00000000000000000000000000000000 + assign \read_en$424 $427 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $385 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $386 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $431 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [4] + connect \A \rdpick_INT_rbc_o [1] connect \B \rdpick_INT_rbc_en_o - connect \Y $385 + connect \Y $431 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - wire width 32 $387 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - cell $sshl $388 + process $group_205 + assign \fus_src2_i$54 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $431 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + case 1'1 + assign \fus_src2_i$54 \int_src3__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $433 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_reg2 - connect \Y $387 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$33 [1] + connect \B \fu_enable [3] + connect \Y $433 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $389 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $435 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [5] - connect \B \rdpick_INT_rbc_en_o - connect \Y $389 + connect \A $433 + connect \B \rdflag_INT_rbc_0 + connect \Y $435 + end + process $group_206 + assign \pick$403 1'0 + assign \pick$403 $435 + sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$437 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - wire width 32 $391 + wire width 32 $438 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - cell $sshl $392 + cell $sshl $439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -159849,504 +160106,428 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \pdecode2_reg2 - connect \Y $391 + connect \Y $438 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $393 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $440 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $441 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [6] + connect \A \rdpick_INT_rbc_o [2] connect \B \rdpick_INT_rbc_en_o - connect \Y $393 + connect \Y $441 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - wire width 32 $395 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - cell $sshl $396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_reg2 - connect \Y $395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $443 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $438 + connect \S $441 + connect \Y $440 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $397 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $398 + process $group_207 + assign \read_en$437 32'00000000000000000000000000000000 + assign \read_en$437 $440 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [7] + connect \A \rdpick_INT_rbc_o [2] connect \B \rdpick_INT_rbc_en_o - connect \Y $397 + connect \Y $444 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - wire width 32 $399 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" - cell $sshl $400 + process $group_208 + assign \fus_src2_i$55 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $444 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + case 1'1 + assign \fus_src2_i$55 \int_src3__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $446 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_reg2 - connect \Y $399 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$36 [1] + connect \B \fu_enable [4] + connect \Y $446 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $401 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $448 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [8] - connect \B \rdpick_INT_rbc_en_o - connect \Y $401 + connect \A $446 + connect \B \rdflag_INT_rbc_0 + connect \Y $448 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55" - wire width 32 $403 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55" - cell $sshl $404 + process $group_209 + assign \pick$404 1'0 + assign \pick$404 $448 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$450 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" + wire width 32 $451 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" + cell $sshl $452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 32 connect \A 1'1 - connect \B \pdecode2_reg3 - connect \Y $403 + connect \B \pdecode2_reg2 + connect \Y $451 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $405 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $453 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $454 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [9] + connect \A \rdpick_INT_rbc_o [3] connect \B \rdpick_INT_rbc_en_o - connect \Y $405 + connect \Y $454 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55" - wire width 32 $407 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55" - cell $sshl $408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_reg3 - connect \Y $407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $456 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $451 + connect \S $454 + connect \Y $453 end - process $group_192 - assign \int_src3__ren 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $369 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src3__ren $371 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $373 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src3__ren $375 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $377 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src3__ren $379 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $381 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src3__ren $383 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $385 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src3__ren $387 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $389 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src3__ren $391 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $393 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src3__ren $395 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $397 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src3__ren $399 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $401 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src3__ren $403 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $405 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \int_src3__ren $407 - end + process $group_210 + assign \read_en$450 32'00000000000000000000000000000000 + assign \read_en$450 $453 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $409 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [0] + connect \A \rdpick_INT_rbc_o [3] connect \B \rdpick_INT_rbc_en_o - connect \Y $409 + connect \Y $457 end - process $group_193 - assign \fus_src2_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $409 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + process $group_211 + assign \fus_src2_i$56 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $457 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 - assign \fus_src2_i \int_src3__data_o + assign \fus_src2_i$56 \int_src3__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $411 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $412 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $459 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$30 [1] - connect \B \fu_enable [1] - connect \Y $411 + connect \A \fus_cu_rd__rel_o$42 [1] + connect \B \fu_enable [6] + connect \Y $459 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $413 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $414 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $461 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $411 + connect \A $459 connect \B \rdflag_INT_rbc_0 - connect \Y $413 + connect \Y $461 end - process $group_194 - assign \pick$360 1'0 - assign \pick$360 $413 + process $group_212 + assign \pick$405 1'0 + assign \pick$405 $461 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $415 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $416 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$463 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" + wire width 32 $464 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" + cell $sshl $465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [1] - connect \B \rdpick_INT_rbc_en_o - connect \Y $415 - end - process $group_195 - assign \fus_src2_i$54 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $415 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fus_src2_i$54 \int_src3__data_o - end - sync init + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_reg2 + connect \Y $464 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $417 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $418 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$33 [1] - connect \B \fu_enable [3] - connect \Y $417 + connect \A \rdpick_INT_rbc_o [4] + connect \B \rdpick_INT_rbc_en_o + connect \Y $467 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $419 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $417 - connect \B \rdflag_INT_rbc_0 - connect \Y $419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $469 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $464 + connect \S $467 + connect \Y $466 end - process $group_196 - assign \pick$361 1'0 - assign \pick$361 $419 + process $group_213 + assign \read_en$463 32'00000000000000000000000000000000 + assign \read_en$463 $466 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $421 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $470 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [2] + connect \A \rdpick_INT_rbc_o [4] connect \B \rdpick_INT_rbc_en_o - connect \Y $421 + connect \Y $470 end - process $group_197 - assign \fus_src2_i$55 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $421 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + process $group_214 + assign \fus_src2_i$57 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $470 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 - assign \fus_src2_i$55 \int_src3__data_o + assign \fus_src2_i$57 \int_src3__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $423 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$36 [1] - connect \B \fu_enable [4] - connect \Y $423 + connect \A \fus_cu_rd__rel_o$45 [1] + connect \B \fu_enable [7] + connect \Y $472 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $425 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $426 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $474 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $423 + connect \A $472 connect \B \rdflag_INT_rbc_0 - connect \Y $425 + connect \Y $474 end - process $group_198 - assign \pick$362 1'0 - assign \pick$362 $425 + process $group_215 + assign \pick$406 1'0 + assign \pick$406 $474 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $427 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $428 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$476 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" + wire width 32 $477 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" + cell $sshl $478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_reg2 + connect \Y $477 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $479 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $480 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [3] + connect \A \rdpick_INT_rbc_o [5] connect \B \rdpick_INT_rbc_en_o - connect \Y $427 + connect \Y $480 end - process $group_199 - assign \fus_src2_i$56 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $427 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fus_src2_i$56 \int_src3__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $429 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$42 [1] - connect \B \fu_enable [6] - connect \Y $429 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $431 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $429 - connect \B \rdflag_INT_rbc_0 - connect \Y $431 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $482 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $477 + connect \S $480 + connect \Y $479 end - process $group_200 - assign \pick$363 1'0 - assign \pick$363 $431 + process $group_216 + assign \read_en$476 32'00000000000000000000000000000000 + assign \read_en$476 $479 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $433 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $434 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $483 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [4] + connect \A \rdpick_INT_rbc_o [5] connect \B \rdpick_INT_rbc_en_o - connect \Y $433 + connect \Y $483 end - process $group_201 - assign \fus_src2_i$57 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $433 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + process $group_217 + assign \fus_src2_i$58 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $483 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 - assign \fus_src2_i$57 \int_src3__data_o + assign \fus_src2_i$58 \int_src3__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $435 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $436 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $485 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$45 [1] - connect \B \fu_enable [7] - connect \Y $435 + connect \A \fus_cu_rd__rel_o$48 [1] + connect \B \fu_enable [8] + connect \Y $485 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $437 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $438 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $487 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $435 + connect \A $485 connect \B \rdflag_INT_rbc_0 - connect \Y $437 + connect \Y $487 end - process $group_202 - assign \pick$364 1'0 - assign \pick$364 $437 + process $group_218 + assign \pick$407 1'0 + assign \pick$407 $487 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $439 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $440 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$489 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" + wire width 32 $490 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" + cell $sshl $491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [5] - connect \B \rdpick_INT_rbc_en_o - connect \Y $439 - end - process $group_203 - assign \fus_src2_i$58 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $439 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fus_src2_i$58 \int_src3__data_o - end - sync init + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_reg2 + connect \Y $490 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $441 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $442 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $492 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $493 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$48 [1] - connect \B \fu_enable [8] - connect \Y $441 + connect \A \rdpick_INT_rbc_o [6] + connect \B \rdpick_INT_rbc_en_o + connect \Y $493 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $443 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $441 - connect \B \rdflag_INT_rbc_0 - connect \Y $443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $495 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $490 + connect \S $493 + connect \Y $492 end - process $group_204 - assign \pick$365 1'0 - assign \pick$365 $443 + process $group_219 + assign \read_en$489 32'00000000000000000000000000000000 + assign \read_en$489 $492 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $445 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $446 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160354,22 +160535,22 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rbc_o [6] connect \B \rdpick_INT_rbc_en_o - connect \Y $445 + connect \Y $496 end - process $group_205 + process $group_220 assign \fus_src2_i$59 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $445 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $496 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src2_i$59 \int_src3__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $447 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $448 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160377,30 +160558,47 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$51 [1] connect \B \fu_enable [9] - connect \Y $447 + connect \Y $498 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $449 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $450 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $500 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $447 + connect \A $498 connect \B \rdflag_INT_rbc_0 - connect \Y $449 + connect \Y $500 end - process $group_206 - assign \pick$366 1'0 - assign \pick$366 $449 + process $group_221 + assign \pick$408 1'0 + assign \pick$408 $500 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $451 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $452 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" + wire width 32 $503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53" + cell $sshl $504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_reg2 + connect \Y $503 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $505 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160408,22 +160606,48 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rbc_o [7] connect \B \rdpick_INT_rbc_en_o - connect \Y $451 + connect \Y $506 end - process $group_207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $508 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $503 + connect \S $506 + connect \Y $505 + end + process $group_222 + assign \read_en$502 32'00000000000000000000000000000000 + assign \read_en$502 $505 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rbc_o [7] + connect \B \rdpick_INT_rbc_en_o + connect \Y $509 + end + process $group_223 assign \fus_src2_i$60 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $451 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $509 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src2_i$60 \int_src3__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $453 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $454 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160431,30 +160655,47 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$48 [2] connect \B \fu_enable [8] - connect \Y $453 + connect \Y $511 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $455 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $456 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $453 + connect \A $511 connect \B \rdflag_INT_rbc_1 - connect \Y $455 + connect \Y $513 end - process $group_208 - assign \pick$367 1'0 - assign \pick$367 $455 + process $group_224 + assign \pick$409 1'0 + assign \pick$409 $513 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $457 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $458 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55" + wire width 32 $516 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55" + cell $sshl $517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_reg3 + connect \Y $516 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160462,22 +160703,48 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rbc_o [8] connect \B \rdpick_INT_rbc_en_o - connect \Y $457 + connect \Y $519 end - process $group_209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $521 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $516 + connect \S $519 + connect \Y $518 + end + process $group_225 + assign \read_en$515 32'00000000000000000000000000000000 + assign \read_en$515 $518 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rbc_o [8] + connect \B \rdpick_INT_rbc_en_o + connect \Y $522 + end + process $group_226 assign \fus_src3_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $457 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $522 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src3_i \int_src3__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $459 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $460 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160485,213 +160752,328 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$51 [2] connect \B \fu_enable [9] - connect \Y $459 + connect \Y $524 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $461 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $462 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $459 + connect \A $524 connect \B \rdflag_INT_rbc_1 - connect \Y $461 + connect \Y $526 end - process $group_210 - assign \pick$368 1'0 - assign \pick$368 $461 + process $group_227 + assign \pick$410 1'0 + assign \pick$410 $526 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $463 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $464 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 32 \read_en$528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55" + wire width 32 $529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55" + cell $sshl $530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rbc_o [9] - connect \B \rdpick_INT_rbc_en_o - connect \Y $463 - end - process $group_211 - assign \fus_src3_i$61 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $463 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fus_src3_i$61 \int_src3__data_o - end - sync init + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_reg3 + connect \Y $529 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" - wire width 1 \rdflag_XER_xer_so_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $465 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $and $466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 32 $531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \pdecode2_oe - connect \B \pdecode2_oe_ok - connect \Y $465 + connect \A \rdpick_INT_rbc_o [9] + connect \B \rdpick_INT_rbc_en_o + connect \Y $532 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $467 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $or $468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $465 - connect \B \pdecode2_xer_in - connect \Y $467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $534 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $529 + connect \S $532 + connect \Y $531 end - process $group_212 - assign \rdflag_XER_xer_so_0 1'0 - assign \rdflag_XER_xer_so_0 $467 + process $group_228 + assign \read_en$528 32'00000000000000000000000000000000 + assign \read_en$528 $531 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$469 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $470 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $471 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [2] - connect \B \fu_enable [0] - connect \Y $470 + connect \A \rdpick_INT_rbc_o [9] + connect \B \rdpick_INT_rbc_en_o + connect \Y $535 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $472 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $473 + process $group_229 + assign \fus_src3_i$61 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $535 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + case 1'1 + assign \fus_src3_i$61 \int_src3__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 32 $537 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $538 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $470 - connect \B \rdflag_XER_xer_so_0 - connect \Y $472 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \read_en$411 + connect \B \read_en$424 + connect \Y $537 end - process $group_213 - assign \pick$469 1'0 - assign \pick$469 $472 - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 32 $539 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \read_en$450 + connect \B \read_en$463 + connect \Y $539 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$474 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$475 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$476 - process $group_214 - assign \rdpick_XER_xer_so_i 4'0000 - assign \rdpick_XER_xer_so_i [0] \pick$469 - assign \rdpick_XER_xer_so_i [1] \pick$474 - assign \rdpick_XER_xer_so_i [2] \pick$475 - assign \rdpick_XER_xer_so_i [3] \pick$476 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 32 $541 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \read_en$437 + connect \B $539 + connect \Y $541 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 32 $543 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $537 + connect \B $541 + connect \Y $543 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 32 $545 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \read_en$476 + connect \B \read_en$489 + connect \Y $545 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 32 $547 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \read_en$515 + connect \B \read_en$528 + connect \Y $547 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 32 $549 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \read_en$502 + connect \B $547 + connect \Y $549 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 32 $551 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $545 + connect \B $549 + connect \Y $551 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 32 $553 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $543 + connect \B $551 + connect \Y $553 + end + process $group_230 + assign \int_src3__ren 32'00000000000000000000000000000000 + assign \int_src3__ren $553 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $477 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $478 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" + wire width 1 \rdflag_XER_xer_so_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + wire width 1 $555 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + cell $and $556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [0] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $477 + connect \A \pdecode2_oe + connect \B \pdecode2_oe_ok + connect \Y $555 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $479 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $480 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + wire width 1 $557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + cell $or $558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [1] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $479 + connect \A $555 + connect \B \pdecode2_xer_in + connect \Y $557 + end + process $group_231 + assign \rdflag_XER_xer_so_0 1'0 + assign \rdflag_XER_xer_so_0 $557 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $481 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $482 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [2] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $481 + connect \A \fus_cu_rd__rel_o [2] + connect \B \fu_enable [0] + connect \Y $560 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $483 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $484 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $562 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [3] + connect \A $560 + connect \B \rdflag_XER_xer_so_0 + connect \Y $562 + end + process $group_232 + assign \pick$559 1'0 + assign \pick$559 $562 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$564 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$566 + process $group_233 + assign \rdpick_XER_xer_so_i 4'0000 + assign \rdpick_XER_xer_so_i [0] \pick$559 + assign \rdpick_XER_xer_so_i [1] \pick$564 + assign \rdpick_XER_xer_so_i [2] \pick$565 + assign \rdpick_XER_xer_so_i [3] \pick$566 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 1 \read_en$567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [0] connect \B \rdpick_XER_xer_so_en_o - connect \Y $483 + connect \Y $569 end - process $group_215 - assign \xer_src1__ren 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $477 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \xer_src1__ren 3'001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $479 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \xer_src1__ren 3'001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $481 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \xer_src1__ren 3'001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $483 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \xer_src1__ren 3'001 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $571 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $569 + connect \Y $568 + end + process $group_234 + assign \read_en$567 1'0 + assign \read_en$567 $568 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $485 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $486 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $572 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160699,22 +161081,22 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [0] connect \B \rdpick_XER_xer_so_en_o - connect \Y $485 + connect \Y $572 end - process $group_216 + process $group_235 assign \fus_src3_i$62 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $485 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $572 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src3_i$62 \xer_src1__data_o [0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $487 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $488 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160722,30 +161104,34 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$39 [3] connect \B \fu_enable [5] - connect \Y $487 + connect \Y $574 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $489 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $490 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $487 + connect \A $574 connect \B \rdflag_XER_xer_so_0 - connect \Y $489 + connect \Y $576 end - process $group_217 - assign \pick$474 1'0 - assign \pick$474 $489 + process $group_236 + assign \pick$564 1'0 + assign \pick$564 $576 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $491 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $492 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 1 \read_en$578 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $580 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160753,22 +161139,48 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [1] connect \B \rdpick_XER_xer_so_en_o - connect \Y $491 + connect \Y $580 end - process $group_218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $582 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $580 + connect \Y $579 + end + process $group_237 + assign \read_en$578 1'0 + assign \read_en$578 $579 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [1] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $583 + end + process $group_238 assign \fus_src4_i 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $491 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $583 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src4_i \xer_src1__data_o [0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $493 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160776,30 +161188,34 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$42 [2] connect \B \fu_enable [6] - connect \Y $493 + connect \Y $585 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $495 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $493 + connect \A $585 connect \B \rdflag_XER_xer_so_0 - connect \Y $495 + connect \Y $587 end - process $group_219 - assign \pick$475 1'0 - assign \pick$475 $495 + process $group_239 + assign \pick$565 1'0 + assign \pick$565 $587 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $497 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 1 \read_en$589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160807,22 +161223,48 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [2] connect \B \rdpick_XER_xer_so_en_o - connect \Y $497 + connect \Y $591 end - process $group_220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $593 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $591 + connect \Y $590 + end + process $group_240 + assign \read_en$589 1'0 + assign \read_en$589 $590 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [2] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $594 + end + process $group_241 assign \fus_src3_i$63 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $497 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $594 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src3_i$63 \xer_src1__data_o [0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $499 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $500 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $596 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160830,30 +161272,34 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$45 [2] connect \B \fu_enable [7] - connect \Y $499 + connect \Y $596 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $501 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $598 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $499 + connect \A $596 connect \B \rdflag_XER_xer_so_0 - connect \Y $501 + connect \Y $598 end - process $group_221 - assign \pick$476 1'0 - assign \pick$476 $501 + process $group_242 + assign \pick$566 1'0 + assign \pick$566 $598 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $503 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $504 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 1 \read_en$600 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $602 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160861,57 +161307,137 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [3] connect \B \rdpick_XER_xer_so_en_o - connect \Y $503 + connect \Y $602 end - process $group_222 - assign \fus_src3_i$64 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $503 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fus_src3_i$64 \xer_src1__data_o [0] - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $604 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $602 + connect \Y $601 + end + process $group_243 + assign \read_en$600 1'0 + assign \read_en$600 $601 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" - wire width 1 \rdflag_XER_xer_ca_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $505 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $eq $506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $606 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [3] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $605 + end + process $group_244 + assign \fus_src3_i$64 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $605 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + case 1'1 + assign \fus_src3_i$64 \xer_src1__data_o [0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 $607 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $608 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \read_en$567 + connect \B \read_en$578 + connect \Y $608 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $610 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \read_en$589 + connect \B \read_en$600 + connect \Y $610 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 1 $612 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $608 + connect \B $610 + connect \Y $612 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A $612 + connect \Y $607 + end + process $group_245 + assign \xer_src1__ren 3'000 + assign \xer_src1__ren $607 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" + wire width 1 \rdflag_XER_xer_ca_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + wire width 1 $615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + cell $eq $616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \pdecode2_input_carry connect \B 2'10 - connect \Y $505 + connect \Y $615 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $507 + wire width 1 $617 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $or $508 + cell $or $618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $505 + connect \A $615 connect \B \pdecode2_xer_in - connect \Y $507 + connect \Y $617 end - process $group_223 + process $group_246 assign \rdflag_XER_xer_ca_0 1'0 - assign \rdflag_XER_xer_ca_0 $507 + assign \rdflag_XER_xer_ca_0 $617 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$509 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $510 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $511 + wire width 1 \pick$619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160919,41 +161445,45 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [3] connect \B \fu_enable [0] - connect \Y $510 + connect \Y $620 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $512 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $622 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $510 + connect \A $620 connect \B \rdflag_XER_xer_ca_0 - connect \Y $512 + connect \Y $622 end - process $group_224 - assign \pick$509 1'0 - assign \pick$509 $512 + process $group_247 + assign \pick$619 1'0 + assign \pick$619 $622 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$514 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$515 - process $group_225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$624 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$625 + process $group_248 assign \rdpick_XER_xer_ca_i 3'000 - assign \rdpick_XER_xer_ca_i [0] \pick$509 - assign \rdpick_XER_xer_ca_i [1] \pick$514 - assign \rdpick_XER_xer_ca_i [2] \pick$515 + assign \rdpick_XER_xer_ca_i [0] \pick$619 + assign \rdpick_XER_xer_ca_i [1] \pick$624 + assign \rdpick_XER_xer_ca_i [2] \pick$625 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $516 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $517 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 2 \read_en$626 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 2 $627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -160961,60 +161491,25 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [0] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $516 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $518 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_ca_o [1] - connect \B \rdpick_XER_xer_ca_en_o - connect \Y $518 + connect \Y $628 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $520 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_ca_o [2] - connect \B \rdpick_XER_xer_ca_en_o - connect \Y $520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $630 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S $628 + connect \Y $627 end - process $group_226 - assign \xer_src2__ren 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $516 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \xer_src2__ren 3'010 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $518 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \xer_src2__ren 3'010 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $520 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \xer_src2__ren 3'010 - end + process $group_249 + assign \read_en$626 2'00 + assign \read_en$626 $627 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $522 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161022,22 +161517,22 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [0] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $522 + connect \Y $631 end - process $group_227 + process $group_250 assign \fus_src4_i$65 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $522 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $631 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src4_i$65 \xer_src2__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $524 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161045,30 +161540,34 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$39 [5] connect \B \fu_enable [5] - connect \Y $524 + connect \Y $633 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $526 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $524 + connect \A $633 connect \B \rdflag_XER_xer_ca_0 - connect \Y $526 + connect \Y $635 end - process $group_228 - assign \pick$514 1'0 - assign \pick$514 $526 + process $group_251 + assign \pick$624 1'0 + assign \pick$624 $635 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $528 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 2 \read_en$637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 2 $638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161076,22 +161575,48 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [1] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $528 + connect \Y $639 end - process $group_229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $641 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S $639 + connect \Y $638 + end + process $group_252 + assign \read_en$637 2'00 + assign \read_en$637 $638 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_ca_o [1] + connect \B \rdpick_XER_xer_ca_en_o + connect \Y $642 + end + process $group_253 assign \fus_src6_i 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $528 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $642 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src6_i \xer_src2__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $530 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161099,30 +161624,60 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$48 [3] connect \B \fu_enable [8] - connect \Y $530 + connect \Y $644 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $532 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $530 + connect \A $644 connect \B \rdflag_XER_xer_ca_0 - connect \Y $532 + connect \Y $646 end - process $group_230 - assign \pick$515 1'0 - assign \pick$515 $532 + process $group_254 + assign \pick$625 1'0 + assign \pick$625 $646 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 2 \read_en$648 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 2 $649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_ca_o [2] + connect \B \rdpick_XER_xer_ca_en_o + connect \Y $650 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $652 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S $650 + connect \Y $649 + end + process $group_255 + assign \read_en$648 2'00 + assign \read_en$648 $649 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $534 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161130,24 +161685,65 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [2] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $534 + connect \Y $653 end - process $group_231 + process $group_256 assign \fus_src4_i$66 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $534 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $653 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src4_i$66 \xer_src2__data_o end sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 $655 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $656 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \read_en$637 + connect \B \read_en$648 + connect \Y $656 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 $658 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \read_en$626 + connect \B $656 + connect \Y $658 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A $658 + connect \Y $655 + end + process $group_257 + assign \xer_src2__ren 3'000 + assign \xer_src2__ren $655 + sync init + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" wire width 1 \rdflag_XER_xer_ov_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $536 + wire width 1 $661 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $537 + cell $and $662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161155,32 +161751,32 @@ module \core parameter \Y_WIDTH 1 connect \A \pdecode2_oe connect \B \pdecode2_oe_ok - connect \Y $536 + connect \Y $661 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $538 + wire width 1 $663 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $539 + cell $or $664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $536 + connect \A $661 connect \B \pdecode2_xer_in - connect \Y $538 + connect \Y $663 end - process $group_232 + process $group_258 assign \rdflag_XER_xer_ov_0 1'0 - assign \rdflag_XER_xer_ov_0 $538 + assign \rdflag_XER_xer_ov_0 $663 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$540 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $541 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $542 + wire width 1 \pick$665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161188,35 +161784,39 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$39 [4] connect \B \fu_enable [5] - connect \Y $541 + connect \Y $666 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $543 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $541 + connect \A $666 connect \B \rdflag_XER_xer_ov_0 - connect \Y $543 + connect \Y $668 end - process $group_233 - assign \pick$540 1'0 - assign \pick$540 $543 + process $group_259 + assign \pick$665 1'0 + assign \pick$665 $668 sync init end - process $group_234 + process $group_260 assign \rdpick_XER_xer_ov_i 1'0 - assign \rdpick_XER_xer_ov_i \pick$540 + assign \rdpick_XER_xer_ov_i \pick$665 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $545 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 3 \read_en$670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 3 $671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161224,22 +161824,25 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ov_o connect \B \rdpick_XER_xer_ov_en_o - connect \Y $545 + connect \Y $672 end - process $group_235 - assign \xer_src3__ren 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $545 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \xer_src3__ren 3'100 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $674 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S $672 + connect \Y $671 + end + process $group_261 + assign \read_en$670 3'000 + assign \read_en$670 $671 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $547 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161247,31 +161850,36 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ov_o connect \B \rdpick_XER_xer_ov_en_o - connect \Y $547 + connect \Y $675 end - process $group_236 + process $group_262 assign \fus_src5_i 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $547 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $675 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src5_i \xer_src3__data_o end sync init end + process $group_263 + assign \xer_src3__ren 3'000 + assign \xer_src3__ren \read_en$670 + sync init + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" wire width 1 \rdflag_CR_full_cr_0 - process $group_237 + process $group_264 assign \rdflag_CR_full_cr_0 1'0 assign \rdflag_CR_full_cr_0 \pdecode2_read_cr_whole sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$549 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $550 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $551 + wire width 1 \pick$677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $678 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161279,35 +161887,39 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$30 [2] connect \B \fu_enable [1] - connect \Y $550 + connect \Y $678 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $552 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $550 + connect \A $678 connect \B \rdflag_CR_full_cr_0 - connect \Y $552 + connect \Y $680 end - process $group_238 - assign \pick$549 1'0 - assign \pick$549 $552 + process $group_265 + assign \pick$677 1'0 + assign \pick$677 $680 sync init end - process $group_239 + process $group_266 assign \rdpick_CR_full_cr_i 1'0 - assign \rdpick_CR_full_cr_i \pick$549 + assign \rdpick_CR_full_cr_i \pick$677 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $554 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $555 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 8 \read_en$682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 8 $683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161315,22 +161927,25 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_full_cr_o connect \B \rdpick_CR_full_cr_en_o - connect \Y $554 + connect \Y $684 end - process $group_240 - assign \cr_full_rd__ren 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $554 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \cr_full_rd__ren 8'11111111 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $686 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B 8'11111111 + connect \S $684 + connect \Y $683 + end + process $group_267 + assign \read_en$682 8'00000000 + assign \read_en$682 $683 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $556 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161338,31 +161953,36 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_full_cr_o connect \B \rdpick_CR_full_cr_en_o - connect \Y $556 + connect \Y $687 end - process $group_241 + process $group_268 assign \fus_src3_i$67 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $556 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $687 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src3_i$67 \cr_full_rd__data_o end sync init end + process $group_269 + assign \cr_full_rd__ren 8'00000000 + assign \cr_full_rd__ren \read_en$682 + sync init + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" wire width 1 \rdflag_CR_cr_a_0 - process $group_242 + process $group_270 assign \rdflag_CR_cr_a_0 1'0 assign \rdflag_CR_cr_a_0 \pdecode2_cr_in1_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$558 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $559 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $560 + wire width 1 \pick$689 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161370,53 +161990,40 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$30 [3] connect \B \fu_enable [1] - connect \Y $559 + connect \Y $690 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $561 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $562 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $559 + connect \A $690 connect \B \rdflag_CR_cr_a_0 - connect \Y $561 + connect \Y $692 end - process $group_243 - assign \pick$558 1'0 - assign \pick$558 $561 + process $group_271 + assign \pick$689 1'0 + assign \pick$689 $692 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$563 - process $group_244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$694 + process $group_272 assign \rdpick_CR_cr_a_i 2'00 - assign \rdpick_CR_cr_a_i [0] \pick$558 - assign \rdpick_CR_cr_a_i [1] \pick$563 + assign \rdpick_CR_cr_a_i [0] \pick$689 + assign \rdpick_CR_cr_a_i [1] \pick$694 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $564 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_a_o [0] - connect \B \rdpick_CR_cr_a_en_o - connect \Y $564 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - wire width 16 $566 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 16 \read_en$695 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - wire width 4 $567 + wire width 4 $696 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - cell $sub $568 + cell $sub $697 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -161424,84 +162031,53 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \pdecode2_cr_in1 - connect \Y $567 + connect \Y $696 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - wire width 16 $569 + wire width 16 $698 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - cell $sshl $570 + cell $sshl $699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $567 - connect \Y $569 + connect \B $696 + connect \Y $698 end - connect $566 $569 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $571 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $572 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 16 $700 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_a_o [1] + connect \A \rdpick_CR_cr_a_o [0] connect \B \rdpick_CR_cr_a_en_o - connect \Y $571 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - wire width 16 $573 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - wire width 4 $574 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - cell $sub $575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_in1 - connect \Y $574 + connect \Y $701 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - wire width 16 $576 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - cell $sshl $577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $574 - connect \Y $576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $703 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $698 + connect \S $701 + connect \Y $700 end - connect $573 $576 - process $group_245 - assign \cr_src1__ren 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $564 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \cr_src1__ren $566 [7:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $571 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \cr_src1__ren $573 [7:0] - end + process $group_273 + assign \read_en$695 16'0000000000000000 + assign \read_en$695 $700 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $578 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161509,22 +162085,22 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [0] connect \B \rdpick_CR_cr_a_en_o - connect \Y $578 + connect \Y $704 end - process $group_246 + process $group_274 assign \fus_src4_i$68 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $578 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $704 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src4_i$68 \cr_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $580 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161532,37 +162108,93 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$69 [2] connect \B \fu_enable [2] - connect \Y $580 + connect \Y $706 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $582 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $708 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $580 + connect \A $706 connect \B \rdflag_CR_cr_a_0 - connect \Y $582 + connect \Y $708 end - process $group_247 - assign \pick$563 1'0 - assign \pick$563 $582 + process $group_275 + assign \pick$694 1'0 + assign \pick$694 $708 sync init end - process $group_248 + process $group_276 assign \fus_cu_rd__go_i$70 3'000 assign \fus_cu_rd__go_i$70 [2] \rdpick_CR_cr_a_o [1] assign \fus_cu_rd__go_i$70 [0] \rdpick_FAST_fast1_o [0] assign \fus_cu_rd__go_i$70 [1] \rdpick_FAST_fast1_o [3] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $584 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 16 \read_en$710 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" + wire width 4 $711 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" + cell $sub $712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \pdecode2_cr_in1 + connect \Y $711 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" + wire width 16 $713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" + cell $sshl $714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $711 + connect \Y $713 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 16 $715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_CR_cr_a_o [1] + connect \B \rdpick_CR_cr_a_en_o + connect \Y $716 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $718 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $713 + connect \S $716 + connect \Y $715 + end + process $group_277 + assign \read_en$710 16'0000000000000000 + assign \read_en$710 $715 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161570,31 +162202,52 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [1] connect \B \rdpick_CR_cr_a_en_o - connect \Y $584 + connect \Y $719 end - process $group_249 + process $group_278 assign \fus_src3_i$71 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $584 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $719 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src3_i$71 \cr_src1__data_o end sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 16 $721 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 16 $722 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \read_en$695 + connect \B \read_en$710 + connect \Y $722 + end + connect $721 $722 + process $group_279 + assign \cr_src1__ren 8'00000000 + assign \cr_src1__ren $721 [7:0] + sync init + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" wire width 1 \rdflag_CR_cr_b_0 - process $group_250 + process $group_280 assign \rdflag_CR_cr_b_0 1'0 assign \rdflag_CR_cr_b_0 \pdecode2_cr_in2_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$586 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $587 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $588 + wire width 1 \pick$724 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161602,50 +162255,37 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$30 [4] connect \B \fu_enable [1] - connect \Y $587 + connect \Y $725 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $589 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $587 + connect \A $725 connect \B \rdflag_CR_cr_b_0 - connect \Y $589 + connect \Y $727 end - process $group_251 - assign \pick$586 1'0 - assign \pick$586 $589 + process $group_281 + assign \pick$724 1'0 + assign \pick$724 $727 sync init end - process $group_252 + process $group_282 assign \rdpick_CR_cr_b_i 1'0 - assign \rdpick_CR_cr_b_i \pick$586 + assign \rdpick_CR_cr_b_i \pick$724 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $591 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_b_o - connect \B \rdpick_CR_cr_b_en_o - connect \Y $591 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" - wire width 16 $593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 16 \read_en$729 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" - wire width 4 $594 + wire width 4 $730 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" - cell $sub $595 + cell $sub $731 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -161653,36 +162293,53 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \pdecode2_cr_in2 - connect \Y $594 + connect \Y $730 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" - wire width 16 $596 + wire width 16 $732 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" - cell $sshl $597 + cell $sshl $733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $594 - connect \Y $596 + connect \B $730 + connect \Y $732 end - connect $593 $596 - process $group_253 - assign \cr_src2__ren 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $591 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \cr_src2__ren $593 [7:0] - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 16 $734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $735 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_CR_cr_b_o + connect \B \rdpick_CR_cr_b_en_o + connect \Y $735 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $737 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $732 + connect \S $735 + connect \Y $734 + end + process $group_283 + assign \read_en$729 16'0000000000000000 + assign \read_en$729 $734 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $598 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $738 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161690,31 +162347,36 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_b_o connect \B \rdpick_CR_cr_b_en_o - connect \Y $598 + connect \Y $738 end - process $group_254 + process $group_284 assign \fus_src5_i$72 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $598 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $738 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src5_i$72 \cr_src2__data_o end sync init end + process $group_285 + assign \cr_src2__ren 8'00000000 + assign \cr_src2__ren \read_en$729 [7:0] + sync init + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" wire width 1 \rdflag_CR_cr_c_0 - process $group_255 + process $group_286 assign \rdflag_CR_cr_c_0 1'0 assign \rdflag_CR_cr_c_0 \pdecode2_cr_in2_ok$1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$600 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $601 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $602 + wire width 1 \pick$740 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $741 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161722,50 +162384,37 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$30 [5] connect \B \fu_enable [1] - connect \Y $601 + connect \Y $741 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $603 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $743 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $601 + connect \A $741 connect \B \rdflag_CR_cr_c_0 - connect \Y $603 + connect \Y $743 end - process $group_256 - assign \pick$600 1'0 - assign \pick$600 $603 + process $group_287 + assign \pick$740 1'0 + assign \pick$740 $743 sync init end - process $group_257 + process $group_288 assign \rdpick_CR_cr_c_i 1'0 - assign \rdpick_CR_cr_c_i \pick$600 + assign \rdpick_CR_cr_c_i \pick$740 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $605 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_c_o - connect \B \rdpick_CR_cr_c_en_o - connect \Y $605 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 16 \read_en$745 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" - wire width 16 $607 + wire width 4 $746 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" - wire width 4 $608 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" - cell $sub $609 + cell $sub $747 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -161773,36 +162422,53 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \pdecode2_cr_in2$2 - connect \Y $608 + connect \Y $746 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" - wire width 16 $610 + wire width 16 $748 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" - cell $sshl $611 + cell $sshl $749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $608 - connect \Y $610 + connect \B $746 + connect \Y $748 end - connect $607 $610 - process $group_258 - assign \cr_src3__ren 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $605 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \cr_src3__ren $607 [7:0] - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 16 $750 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_CR_cr_c_o + connect \B \rdpick_CR_cr_c_en_o + connect \Y $751 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $753 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $748 + connect \S $751 + connect \Y $750 + end + process $group_289 + assign \read_en$745 16'0000000000000000 + assign \read_en$745 $750 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $612 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161810,38 +162476,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_c_o connect \B \rdpick_CR_cr_c_en_o - connect \Y $612 + connect \Y $754 end - process $group_259 + process $group_290 assign \fus_src6_i$73 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $612 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $754 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src6_i$73 \cr_src3__data_o end sync init end + process $group_291 + assign \cr_src3__ren 8'00000000 + assign \cr_src3__ren \read_en$745 [7:0] + sync init + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" wire width 1 \rdflag_FAST_fast1_0 - process $group_260 + process $group_292 assign \rdflag_FAST_fast1_0 1'0 assign \rdflag_FAST_fast1_0 \pdecode2_fast1_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" wire width 1 \rdflag_FAST_fast1_1 - process $group_261 + process $group_293 assign \rdflag_FAST_fast1_1 1'0 assign \rdflag_FAST_fast1_1 \pdecode2_fast2_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$614 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $615 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $616 + wire width 1 \pick$756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161849,62 +162520,49 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$69 [0] connect \B \fu_enable [2] - connect \Y $615 + connect \Y $757 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $617 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $618 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $759 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $615 + connect \A $757 connect \B \rdflag_FAST_fast1_0 - connect \Y $617 - end - process $group_262 - assign \pick$614 1'0 - assign \pick$614 $617 - sync init + connect \Y $759 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$619 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$620 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$621 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$622 - process $group_263 - assign \rdpick_FAST_fast1_i 5'00000 - assign \rdpick_FAST_fast1_i [0] \pick$614 - assign \rdpick_FAST_fast1_i [1] \pick$619 - assign \rdpick_FAST_fast1_i [2] \pick$620 - assign \rdpick_FAST_fast1_i [3] \pick$621 - assign \rdpick_FAST_fast1_i [4] \pick$622 + process $group_294 + assign \pick$756 1'0 + assign \pick$756 $759 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $623 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [0] - connect \B \rdpick_FAST_fast1_en_o - connect \Y $623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$761 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$762 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$763 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \pick$764 + process $group_295 + assign \rdpick_FAST_fast1_i 5'00000 + assign \rdpick_FAST_fast1_i [0] \pick$756 + assign \rdpick_FAST_fast1_i [1] \pick$761 + assign \rdpick_FAST_fast1_i [2] \pick$762 + assign \rdpick_FAST_fast1_i [3] \pick$763 + assign \rdpick_FAST_fast1_i [4] \pick$764 + sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 8 \read_en$765 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - wire width 8 $625 + wire width 8 $766 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - wire width 8 $626 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - cell $sshl $627 + cell $sshl $767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -161912,271 +162570,234 @@ module \core parameter \Y_WIDTH 8 connect \A 1'1 connect \B \pdecode2_fast1 - connect \Y $626 + connect \Y $766 end - connect $625 $626 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $628 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 8 $768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [1] + connect \A \rdpick_FAST_fast1_o [0] connect \B \rdpick_FAST_fast1_en_o - connect \Y $628 + connect \Y $769 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - wire width 8 $630 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - wire width 8 $631 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - cell $sshl $632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fast1 - connect \Y $631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $771 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B $766 + connect \S $769 + connect \Y $768 end - connect $630 $631 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $633 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $634 + process $group_296 + assign \read_en$765 8'00000000 + assign \read_en$765 $768 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [2] + connect \A \rdpick_FAST_fast1_o [0] connect \B \rdpick_FAST_fast1_en_o - connect \Y $633 + connect \Y $772 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - wire width 8 $635 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - wire width 8 $636 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - cell $sshl $637 + process $group_297 + assign \fus_src1_i$74 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $772 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + case 1'1 + assign \fus_src1_i$74 \fast_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $774 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fast1 - connect \Y $636 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$33 [2] + connect \B \fu_enable [3] + connect \Y $774 end - connect $635 $636 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $638 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [3] - connect \B \rdpick_FAST_fast1_en_o - connect \Y $638 + connect \A $774 + connect \B \rdflag_FAST_fast1_0 + connect \Y $776 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" - wire width 8 $640 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" - wire width 8 $641 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" - cell $sshl $642 + process $group_298 + assign \pick$761 1'0 + assign \pick$761 $776 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 8 \read_en$778 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" + wire width 8 $779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" + cell $sshl $780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 8 connect \A 1'1 - connect \B \pdecode2_fast2 - connect \Y $641 + connect \B \pdecode2_fast1 + connect \Y $779 end - connect $640 $641 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $643 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 8 $781 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $782 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [4] + connect \A \rdpick_FAST_fast1_o [1] connect \B \rdpick_FAST_fast1_en_o - connect \Y $643 + connect \Y $782 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" - wire width 8 $645 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" - wire width 8 $646 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" - cell $sshl $647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fast2 - connect \Y $646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $784 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B $779 + connect \S $782 + connect \Y $781 end - connect $645 $646 - process $group_264 - assign \fast_src1__ren 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $623 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fast_src1__ren $625 [4:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $628 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fast_src1__ren $630 [4:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $633 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fast_src1__ren $635 [4:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $638 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fast_src1__ren $640 [4:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $643 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fast_src1__ren $645 [4:0] - end + process $group_299 + assign \read_en$778 8'00000000 + assign \read_en$778 $781 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $648 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $785 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [0] + connect \A \rdpick_FAST_fast1_o [1] connect \B \rdpick_FAST_fast1_en_o - connect \Y $648 + connect \Y $785 end - process $group_265 - assign \fus_src1_i$74 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $648 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + process $group_300 + assign \fus_src3_i$75 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $785 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 - assign \fus_src1_i$74 \fast_src1__data_o + assign \fus_src3_i$75 \fast_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $650 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$33 [2] - connect \B \fu_enable [3] - connect \Y $650 + connect \A \fus_cu_rd__rel_o$39 [2] + connect \B \fu_enable [5] + connect \Y $787 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $652 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $789 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $650 + connect \A $787 connect \B \rdflag_FAST_fast1_0 - connect \Y $652 + connect \Y $789 end - process $group_266 - assign \pick$619 1'0 - assign \pick$619 $652 + process $group_301 + assign \pick$762 1'0 + assign \pick$762 $789 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $654 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 8 \read_en$791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" + wire width 8 $792 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" + cell $sshl $793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [1] - connect \B \rdpick_FAST_fast1_en_o - connect \Y $654 - end - process $group_267 - assign \fus_src3_i$75 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $654 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fus_src3_i$75 \fast_src1__data_o - end - sync init + parameter \B_WIDTH 3 + parameter \Y_WIDTH 8 + connect \A 1'1 + connect \B \pdecode2_fast1 + connect \Y $792 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $656 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 8 $794 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $795 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$39 [2] - connect \B \fu_enable [5] - connect \Y $656 + connect \A \rdpick_FAST_fast1_o [2] + connect \B \rdpick_FAST_fast1_en_o + connect \Y $795 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $658 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $656 - connect \B \rdflag_FAST_fast1_0 - connect \Y $658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $797 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B $792 + connect \S $795 + connect \Y $794 end - process $group_268 - assign \pick$620 1'0 - assign \pick$620 $658 + process $group_302 + assign \read_en$791 8'00000000 + assign \read_en$791 $794 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $660 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $798 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162184,22 +162805,22 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [2] connect \B \rdpick_FAST_fast1_en_o - connect \Y $660 + connect \Y $798 end - process $group_269 + process $group_303 assign \fus_src3_i$76 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $660 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $798 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src3_i$76 \fast_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $662 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $800 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162207,30 +162828,47 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$69 [1] connect \B \fu_enable [2] - connect \Y $662 + connect \Y $800 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $664 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $802 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $662 + connect \A $800 connect \B \rdflag_FAST_fast1_1 - connect \Y $664 + connect \Y $802 end - process $group_270 - assign \pick$621 1'0 - assign \pick$621 $664 + process $group_304 + assign \pick$763 1'0 + assign \pick$763 $802 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $666 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 8 \read_en$804 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" + wire width 8 $805 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" + cell $sshl $806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 8 + connect \A 1'1 + connect \B \pdecode2_fast2 + connect \Y $805 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 8 $807 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $808 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162238,22 +162876,48 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [3] connect \B \rdpick_FAST_fast1_en_o - connect \Y $666 + connect \Y $808 end - process $group_271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $810 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B $805 + connect \S $808 + connect \Y $807 + end + process $group_305 + assign \read_en$804 8'00000000 + assign \read_en$804 $807 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $811 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_FAST_fast1_o [3] + connect \B \rdpick_FAST_fast1_en_o + connect \Y $811 + end + process $group_306 assign \fus_src2_i$77 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $666 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $811 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src2_i$77 \fast_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $668 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162261,30 +162925,47 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$33 [3] connect \B \fu_enable [3] - connect \Y $668 + connect \Y $813 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $670 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $668 + connect \A $813 connect \B \rdflag_FAST_fast1_1 - connect \Y $670 + connect \Y $815 end - process $group_272 - assign \pick$622 1'0 - assign \pick$622 $670 + process $group_307 + assign \pick$764 1'0 + assign \pick$764 $815 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $672 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 8 \read_en$817 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" + wire width 8 $818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" + cell $sshl $819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 8 + connect \A 1'1 + connect \B \pdecode2_fast2 + connect \Y $818 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 8 $820 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $821 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162292,69 +162973,157 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [4] connect \B \rdpick_FAST_fast1_en_o - connect \Y $672 + connect \Y $821 end - process $group_273 - assign \fus_src4_i$78 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $672 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign \fus_src4_i$78 \fast_src1__data_o - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $823 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B $818 + connect \S $821 + connect \Y $820 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" - wire width 1 \rdflag_SPR_spr1_0 - process $group_274 - assign \rdflag_SPR_spr1_0 1'0 - assign \rdflag_SPR_spr1_0 \pdecode2_spr1_ok + process $group_308 + assign \read_en$817 8'00000000 + assign \read_en$817 $820 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" - wire width 1 \pick$674 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $675 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $676 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$39 [1] - connect \B \fu_enable [5] - connect \Y $675 + connect \A \rdpick_FAST_fast1_o [4] + connect \B \rdpick_FAST_fast1_en_o + connect \Y $824 + end + process $group_309 + assign \fus_src4_i$78 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $824 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + case 1'1 + assign \fus_src4_i$78 \fast_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 8 $826 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 8 $827 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \read_en$765 + connect \B \read_en$778 + connect \Y $827 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 8 $829 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \read_en$804 + connect \B \read_en$817 + connect \Y $829 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 8 $831 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \read_en$791 + connect \B $829 + connect \Y $831 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 8 $833 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $827 + connect \B $831 + connect \Y $833 + end + connect $826 $833 + process $group_310 + assign \fast_src1__ren 5'00000 + assign \fast_src1__ren $826 [4:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" + wire width 1 \rdflag_SPR_spr1_0 + process $group_311 + assign \rdflag_SPR_spr1_0 1'0 + assign \rdflag_SPR_spr1_0 \pdecode2_spr1_ok + sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 $677 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - cell $and $678 + wire width 1 \pick$835 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $675 + connect \A \fus_cu_rd__rel_o$39 [1] + connect \B \fu_enable [5] + connect \Y $836 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 $838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + cell $and $839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $836 connect \B \rdflag_SPR_spr1_0 - connect \Y $677 + connect \Y $838 end - process $group_275 - assign \pick$674 1'0 - assign \pick$674 $677 + process $group_312 + assign \pick$835 1'0 + assign \pick$835 $838 sync init end - process $group_276 + process $group_313 assign \rdpick_SPR_spr1_i 1'0 - assign \rdpick_SPR_spr1_i \pick$674 + assign \rdpick_SPR_spr1_i \pick$835 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfiles.py:158" - wire width 1 $memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $679 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232" + wire width 10 \read_en$840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 10 $841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + wire width 1 $842 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $and $843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162362,43 +163131,25 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_SPR_spr1_o connect \B \rdpick_SPR_spr1_en_o - connect \Y $679 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $681 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick - connect \B \wrpick_SPR_spr1_en_o - connect \Y $681 + connect \Y $842 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233" + cell $mux $844 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B \pdecode2_spr1 + connect \S $842 + connect \Y $841 end - process $group_277 - assign $memory_w_en 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $679 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - case 1'1 - assign $memory_w_en \pdecode2_spr1 [0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $681 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign $memory_w_en \pdecode2_spro [0] - end + process $group_314 + assign \read_en$840 10'0000000000 + assign \read_en$840 $841 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $683 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $845 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162406,26 +163157,36 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_SPR_spr1_o connect \B \rdpick_SPR_spr1_en_o - connect \Y $683 + connect \Y $845 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfiles.py:158" wire width 64 $memory_w_data - process $group_278 + process $group_315 assign \fus_src2_i$79 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - switch { $683 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + switch { $845 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" case 1'1 assign \fus_src2_i$79 $memory_w_data end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfiles.py:158" + wire width 1 $memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 10 \write_en + process $group_316 + assign $memory_w_en 1'0 + assign $memory_w_en \read_en$840 [0] + assign $memory_w_en \write_en [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_alu0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $685 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $686 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $847 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162433,17 +163194,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok connect \B \fus_cu_busy_o - connect \Y $685 + connect \Y $847 end - process $group_279 + process $group_317 assign \wrflag_alu0_o_0 1'0 - assign \wrflag_alu0_o_0 $685 + assign \wrflag_alu0_o_0 $847 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $687 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $849 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162451,12 +163212,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [0] connect \B \fu_enable [0] - connect \Y $687 + connect \Y $849 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $689 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $851 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162464,12 +163225,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$81 [0] connect \B \fu_enable [1] - connect \Y $689 + connect \Y $851 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $691 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $853 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162477,12 +163238,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$84 [0] connect \B \fu_enable [3] - connect \Y $691 + connect \Y $853 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $693 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $694 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $855 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162490,12 +163251,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$87 [0] connect \B \fu_enable [4] - connect \Y $693 + connect \Y $855 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $695 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $857 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162503,12 +163264,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$90 [0] connect \B \fu_enable [5] - connect \Y $695 + connect \Y $857 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $697 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $698 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $859 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162516,12 +163277,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [0] connect \B \fu_enable [6] - connect \Y $697 + connect \Y $859 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $699 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $700 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $861 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162529,12 +163290,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [0] connect \B \fu_enable [7] - connect \Y $699 + connect \Y $861 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $701 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $863 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162542,12 +163303,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [0] connect \B \fu_enable [8] - connect \Y $701 + connect \Y $863 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $703 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $865 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162555,12 +163316,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$101 [0] connect \B \fu_enable [9] - connect \Y $703 + connect \Y $865 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $705 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $867 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162568,28 +163329,28 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$101 [1] connect \B \fu_enable [9] - connect \Y $705 + connect \Y $867 end - process $group_280 + process $group_318 assign \wrpick_INT_o_i 10'0000000000 - assign \wrpick_INT_o_i [0] $687 - assign \wrpick_INT_o_i [1] $689 - assign \wrpick_INT_o_i [2] $691 - assign \wrpick_INT_o_i [3] $693 - assign \wrpick_INT_o_i [4] $695 - assign \wrpick_INT_o_i [5] $697 - assign \wrpick_INT_o_i [6] $699 - assign \wrpick_INT_o_i [7] $701 - assign \wrpick_INT_o_i [8] $703 - assign \wrpick_INT_o_i [9] $705 + assign \wrpick_INT_o_i [0] $849 + assign \wrpick_INT_o_i [1] $851 + assign \wrpick_INT_o_i [2] $853 + assign \wrpick_INT_o_i [3] $855 + assign \wrpick_INT_o_i [4] $857 + assign \wrpick_INT_o_i [5] $859 + assign \wrpick_INT_o_i [6] $861 + assign \wrpick_INT_o_i [7] $863 + assign \wrpick_INT_o_i [8] $865 + assign \wrpick_INT_o_i [9] $867 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$707 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $708 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $709 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $869 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -162597,20 +163358,20 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [0] connect \B \wrpick_INT_o_en_o - connect \Y $708 + connect \Y $869 end - process $group_281 - assign \wr_pick$707 1'0 - assign \wr_pick$707 $708 + process $group_319 + assign \wr_pick 1'0 + assign \wr_pick $869 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire width 1 \wr_pick_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire width 1 \wr_pick_dly$next - process $group_282 + process $group_320 assign \wr_pick_dly$next \wr_pick_dly - assign \wr_pick_dly$next \wr_pick$707 + assign \wr_pick_dly$next \wr_pick attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 @@ -162624,398 +163385,99 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire width 1 \wr_pick_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $710 + wire width 1 $871 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $711 + cell $not $872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly - connect \Y $710 + connect \Y $871 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $712 + wire width 1 $873 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $713 + cell $and $874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$707 - connect \B $710 - connect \Y $712 + connect \A \wr_pick + connect \B $871 + connect \Y $873 end - process $group_283 + process $group_321 assign \wr_pick_rise 1'0 - assign \wr_pick_rise $712 + assign \wr_pick_rise $873 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$714 + wire width 1 \wr_pick_rise$875 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$715 + wire width 1 \wr_pick_rise$876 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$716 + wire width 1 \wr_pick_rise$877 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$717 - process $group_284 + wire width 1 \wr_pick_rise$878 + process $group_322 assign \fus_cu_wr__go_i 5'00000 assign \fus_cu_wr__go_i [0] \wr_pick_rise - assign \fus_cu_wr__go_i [1] \wr_pick_rise$714 - assign \fus_cu_wr__go_i [2] \wr_pick_rise$715 - assign \fus_cu_wr__go_i [3] \wr_pick_rise$716 - assign \fus_cu_wr__go_i [4] \wr_pick_rise$717 + assign \fus_cu_wr__go_i [1] \wr_pick_rise$875 + assign \fus_cu_wr__go_i [2] \wr_pick_rise$876 + assign \fus_cu_wr__go_i [3] \wr_pick_rise$877 + assign \fus_cu_wr__go_i [4] \wr_pick_rise$878 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $718 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$707 - connect \B \wrpick_INT_o_en_o - connect \Y $718 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - wire width 32 $720 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - cell $sshl $721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_rego - connect \Y $720 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$722 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $723 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$722 - connect \B \wrpick_INT_o_en_o - connect \Y $723 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - wire width 32 $725 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - cell $sshl $726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_rego - connect \Y $725 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$727 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $728 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$727 - connect \B \wrpick_INT_o_en_o - connect \Y $728 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - wire width 32 $730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 32 \write_en$879 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - cell $sshl $731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_rego - connect \Y $730 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$732 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $733 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$732 - connect \B \wrpick_INT_o_en_o - connect \Y $733 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - wire width 32 $735 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - cell $sshl $736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_rego - connect \Y $735 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$737 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $738 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$737 - connect \B \wrpick_INT_o_en_o - connect \Y $738 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - wire width 32 $740 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - cell $sshl $741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_rego - connect \Y $740 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$742 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $743 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$742 - connect \B \wrpick_INT_o_en_o - connect \Y $743 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - wire width 32 $745 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - cell $sshl $746 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_rego - connect \Y $745 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$747 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $748 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$747 - connect \B \wrpick_INT_o_en_o - connect \Y $748 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - wire width 32 $750 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - cell $sshl $751 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_rego - connect \Y $750 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$752 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $753 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$752 - connect \B \wrpick_INT_o_en_o - connect \Y $753 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - wire width 32 $755 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - cell $sshl $756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_rego - connect \Y $755 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$757 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $758 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$757 - connect \B \wrpick_INT_o_en_o - connect \Y $758 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - wire width 32 $760 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" - cell $sshl $761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_rego - connect \Y $760 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$762 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $763 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$762 - connect \B \wrpick_INT_o_en_o - connect \Y $763 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:131" - wire width 32 $765 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:131" - cell $sshl $766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A 1'1 - connect \B \pdecode2_ea - connect \Y $765 - end - process $group_285 - assign \int_wen 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $718 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \int_wen $720 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $723 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \int_wen $725 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $728 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \int_wen $730 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $733 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \int_wen $735 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $738 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \int_wen $740 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $743 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \int_wen $745 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $748 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \int_wen $750 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $753 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \int_wen $755 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $758 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \int_wen $760 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $763 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \int_wen $765 - end + wire width 32 $880 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + cell $sshl $881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_rego + connect \Y $880 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 32 $882 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $883 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick + connect \B \wrpick_INT_o_en_o + connect \Y $883 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $885 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $880 + connect \S $883 + connect \Y $882 + end + process $group_323 + assign \write_en$879 32'00000000000000000000000000000000 + assign \write_en$879 $882 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_cr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $767 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $886 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163023,17 +163485,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$80 connect \B \fus_cu_busy_o$4 - connect \Y $767 + connect \Y $886 end - process $group_286 + process $group_324 assign \wrflag_cr0_o_0 1'0 - assign \wrflag_cr0_o_0 $767 + assign \wrflag_cr0_o_0 $886 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $769 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $770 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$888 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $889 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163041,77 +163505,120 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [1] connect \B \wrpick_INT_o_en_o - connect \Y $769 + connect \Y $889 end - process $group_287 - assign \wr_pick$722 1'0 - assign \wr_pick$722 $769 + process $group_325 + assign \wr_pick$888 1'0 + assign \wr_pick$888 $889 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$771 + wire width 1 \wr_pick_dly$891 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$771$next - process $group_288 - assign \wr_pick_dly$771$next \wr_pick_dly$771 - assign \wr_pick_dly$771$next \wr_pick$722 + wire width 1 \wr_pick_dly$891$next + process $group_326 + assign \wr_pick_dly$891$next \wr_pick_dly$891 + assign \wr_pick_dly$891$next \wr_pick$888 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$771$next 1'0 + assign \wr_pick_dly$891$next 1'0 end sync init - update \wr_pick_dly$771 1'0 + update \wr_pick_dly$891 1'0 sync posedge \coresync_clk - update \wr_pick_dly$771 \wr_pick_dly$771$next + update \wr_pick_dly$891 \wr_pick_dly$891$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$772 + wire width 1 \wr_pick_rise$892 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $773 + wire width 1 $893 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $774 + cell $not $894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$771 - connect \Y $773 + connect \A \wr_pick_dly$891 + connect \Y $893 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $775 + wire width 1 $895 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $776 + cell $and $896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$722 - connect \B $773 - connect \Y $775 + connect \A \wr_pick$888 + connect \B $893 + connect \Y $895 end - process $group_289 - assign \wr_pick_rise$772 1'0 - assign \wr_pick_rise$772 $775 + process $group_327 + assign \wr_pick_rise$892 1'0 + assign \wr_pick_rise$892 $895 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$777 + wire width 1 \wr_pick_rise$897 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$778 - process $group_290 + wire width 1 \wr_pick_rise$898 + process $group_328 assign \fus_cu_wr__go_i$82 3'000 - assign \fus_cu_wr__go_i$82 [0] \wr_pick_rise$772 - assign \fus_cu_wr__go_i$82 [1] \wr_pick_rise$777 - assign \fus_cu_wr__go_i$82 [2] \wr_pick_rise$778 + assign \fus_cu_wr__go_i$82 [0] \wr_pick_rise$892 + assign \fus_cu_wr__go_i$82 [1] \wr_pick_rise$897 + assign \fus_cu_wr__go_i$82 [2] \wr_pick_rise$898 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 32 \write_en$899 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + wire width 32 $900 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + cell $sshl $901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_rego + connect \Y $900 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 32 $902 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $903 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$888 + connect \B \wrpick_INT_o_en_o + connect \Y $903 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $905 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $900 + connect \S $903 + connect \Y $902 + end + process $group_329 + assign \write_en$899 32'00000000000000000000000000000000 + assign \write_en$899 $902 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_trap0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $779 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $780 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $906 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163119,17 +163626,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$83 connect \B \fus_cu_busy_o$10 - connect \Y $779 + connect \Y $906 end - process $group_291 + process $group_330 assign \wrflag_trap0_o_0 1'0 - assign \wrflag_trap0_o_0 $779 + assign \wrflag_trap0_o_0 $906 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $781 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $782 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$908 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $909 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163137,83 +163646,126 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [2] connect \B \wrpick_INT_o_en_o - connect \Y $781 + connect \Y $909 end - process $group_292 - assign \wr_pick$727 1'0 - assign \wr_pick$727 $781 + process $group_331 + assign \wr_pick$908 1'0 + assign \wr_pick$908 $909 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$783 + wire width 1 \wr_pick_dly$911 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$783$next - process $group_293 - assign \wr_pick_dly$783$next \wr_pick_dly$783 - assign \wr_pick_dly$783$next \wr_pick$727 + wire width 1 \wr_pick_dly$911$next + process $group_332 + assign \wr_pick_dly$911$next \wr_pick_dly$911 + assign \wr_pick_dly$911$next \wr_pick$908 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$783$next 1'0 + assign \wr_pick_dly$911$next 1'0 end sync init - update \wr_pick_dly$783 1'0 + update \wr_pick_dly$911 1'0 sync posedge \coresync_clk - update \wr_pick_dly$783 \wr_pick_dly$783$next + update \wr_pick_dly$911 \wr_pick_dly$911$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$784 + wire width 1 \wr_pick_rise$912 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $785 + wire width 1 $913 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $786 + cell $not $914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$783 - connect \Y $785 + connect \A \wr_pick_dly$911 + connect \Y $913 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $787 + wire width 1 $915 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $788 + cell $and $916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$727 - connect \B $785 - connect \Y $787 + connect \A \wr_pick$908 + connect \B $913 + connect \Y $915 end - process $group_294 - assign \wr_pick_rise$784 1'0 - assign \wr_pick_rise$784 $787 + process $group_333 + assign \wr_pick_rise$912 1'0 + assign \wr_pick_rise$912 $915 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$789 + wire width 1 \wr_pick_rise$917 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$790 + wire width 1 \wr_pick_rise$918 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$791 + wire width 1 \wr_pick_rise$919 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$792 - process $group_295 + wire width 1 \wr_pick_rise$920 + process $group_334 assign \fus_cu_wr__go_i$85 5'00000 - assign \fus_cu_wr__go_i$85 [0] \wr_pick_rise$784 - assign \fus_cu_wr__go_i$85 [1] \wr_pick_rise$789 - assign \fus_cu_wr__go_i$85 [2] \wr_pick_rise$790 - assign \fus_cu_wr__go_i$85 [3] \wr_pick_rise$791 - assign \fus_cu_wr__go_i$85 [4] \wr_pick_rise$792 + assign \fus_cu_wr__go_i$85 [0] \wr_pick_rise$912 + assign \fus_cu_wr__go_i$85 [1] \wr_pick_rise$917 + assign \fus_cu_wr__go_i$85 [2] \wr_pick_rise$918 + assign \fus_cu_wr__go_i$85 [3] \wr_pick_rise$919 + assign \fus_cu_wr__go_i$85 [4] \wr_pick_rise$920 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 32 \write_en$921 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + wire width 32 $922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + cell $sshl $923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_rego + connect \Y $922 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 32 $924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $925 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$908 + connect \B \wrpick_INT_o_en_o + connect \Y $925 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $927 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $922 + connect \S $925 + connect \Y $924 + end + process $group_335 + assign \write_en$921 32'00000000000000000000000000000000 + assign \write_en$921 $924 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_logical0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $793 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $794 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $928 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163221,17 +163773,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$86 connect \B \fus_cu_busy_o$13 - connect \Y $793 + connect \Y $928 end - process $group_296 + process $group_336 assign \wrflag_logical0_o_0 1'0 - assign \wrflag_logical0_o_0 $793 + assign \wrflag_logical0_o_0 $928 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $795 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $796 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$930 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $931 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163239,77 +163793,120 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [3] connect \B \wrpick_INT_o_en_o - connect \Y $795 + connect \Y $931 end - process $group_297 - assign \wr_pick$732 1'0 - assign \wr_pick$732 $795 + process $group_337 + assign \wr_pick$930 1'0 + assign \wr_pick$930 $931 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$797 + wire width 1 \wr_pick_dly$933 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$797$next - process $group_298 - assign \wr_pick_dly$797$next \wr_pick_dly$797 - assign \wr_pick_dly$797$next \wr_pick$732 + wire width 1 \wr_pick_dly$933$next + process $group_338 + assign \wr_pick_dly$933$next \wr_pick_dly$933 + assign \wr_pick_dly$933$next \wr_pick$930 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$797$next 1'0 + assign \wr_pick_dly$933$next 1'0 end sync init - update \wr_pick_dly$797 1'0 + update \wr_pick_dly$933 1'0 sync posedge \coresync_clk - update \wr_pick_dly$797 \wr_pick_dly$797$next + update \wr_pick_dly$933 \wr_pick_dly$933$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$798 + wire width 1 \wr_pick_rise$934 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $799 + wire width 1 $935 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $800 + cell $not $936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$797 - connect \Y $799 + connect \A \wr_pick_dly$933 + connect \Y $935 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $801 + wire width 1 $937 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $802 + cell $and $938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$732 - connect \B $799 - connect \Y $801 + connect \A \wr_pick$930 + connect \B $935 + connect \Y $937 end - process $group_299 - assign \wr_pick_rise$798 1'0 - assign \wr_pick_rise$798 $801 + process $group_339 + assign \wr_pick_rise$934 1'0 + assign \wr_pick_rise$934 $937 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$803 + wire width 1 \wr_pick_rise$939 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$804 - process $group_300 + wire width 1 \wr_pick_rise$940 + process $group_340 assign \fus_cu_wr__go_i$88 3'000 - assign \fus_cu_wr__go_i$88 [0] \wr_pick_rise$798 - assign \fus_cu_wr__go_i$88 [1] \wr_pick_rise$803 - assign \fus_cu_wr__go_i$88 [2] \wr_pick_rise$804 + assign \fus_cu_wr__go_i$88 [0] \wr_pick_rise$934 + assign \fus_cu_wr__go_i$88 [1] \wr_pick_rise$939 + assign \fus_cu_wr__go_i$88 [2] \wr_pick_rise$940 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 32 \write_en$941 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + wire width 32 $942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + cell $sshl $943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_rego + connect \Y $942 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 32 $944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $945 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$930 + connect \B \wrpick_INT_o_en_o + connect \Y $945 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $947 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $942 + connect \S $945 + connect \Y $944 + end + process $group_341 + assign \write_en$941 32'00000000000000000000000000000000 + assign \write_en$941 $944 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_spr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $805 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $806 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $948 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163317,17 +163914,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$89 connect \B \fus_cu_busy_o$16 - connect \Y $805 + connect \Y $948 end - process $group_301 + process $group_342 assign \wrflag_spr0_o_0 1'0 - assign \wrflag_spr0_o_0 $805 + assign \wrflag_spr0_o_0 $948 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $807 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $808 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$950 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $951 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163335,86 +163934,129 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [4] connect \B \wrpick_INT_o_en_o - connect \Y $807 + connect \Y $951 end - process $group_302 - assign \wr_pick$737 1'0 - assign \wr_pick$737 $807 + process $group_343 + assign \wr_pick$950 1'0 + assign \wr_pick$950 $951 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$809 + wire width 1 \wr_pick_dly$953 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$809$next - process $group_303 - assign \wr_pick_dly$809$next \wr_pick_dly$809 - assign \wr_pick_dly$809$next \wr_pick$737 + wire width 1 \wr_pick_dly$953$next + process $group_344 + assign \wr_pick_dly$953$next \wr_pick_dly$953 + assign \wr_pick_dly$953$next \wr_pick$950 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$809$next 1'0 + assign \wr_pick_dly$953$next 1'0 end sync init - update \wr_pick_dly$809 1'0 + update \wr_pick_dly$953 1'0 sync posedge \coresync_clk - update \wr_pick_dly$809 \wr_pick_dly$809$next + update \wr_pick_dly$953 \wr_pick_dly$953$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$810 + wire width 1 \wr_pick_rise$954 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $811 + wire width 1 $955 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $812 + cell $not $956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$809 - connect \Y $811 + connect \A \wr_pick_dly$953 + connect \Y $955 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $813 + wire width 1 $957 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $814 + cell $and $958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$737 - connect \B $811 - connect \Y $813 + connect \A \wr_pick$950 + connect \B $955 + connect \Y $957 end - process $group_304 - assign \wr_pick_rise$810 1'0 - assign \wr_pick_rise$810 $813 + process $group_345 + assign \wr_pick_rise$954 1'0 + assign \wr_pick_rise$954 $957 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$815 + wire width 1 \wr_pick_rise$959 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$816 + wire width 1 \wr_pick_rise$960 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$817 + wire width 1 \wr_pick_rise$961 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$818 + wire width 1 \wr_pick_rise$962 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$819 - process $group_305 + wire width 1 \wr_pick_rise$963 + process $group_346 assign \fus_cu_wr__go_i$91 6'000000 - assign \fus_cu_wr__go_i$91 [0] \wr_pick_rise$810 - assign \fus_cu_wr__go_i$91 [5] \wr_pick_rise$815 - assign \fus_cu_wr__go_i$91 [4] \wr_pick_rise$816 - assign \fus_cu_wr__go_i$91 [3] \wr_pick_rise$817 - assign \fus_cu_wr__go_i$91 [2] \wr_pick_rise$818 - assign \fus_cu_wr__go_i$91 [1] \wr_pick_rise$819 + assign \fus_cu_wr__go_i$91 [0] \wr_pick_rise$954 + assign \fus_cu_wr__go_i$91 [5] \wr_pick_rise$959 + assign \fus_cu_wr__go_i$91 [4] \wr_pick_rise$960 + assign \fus_cu_wr__go_i$91 [3] \wr_pick_rise$961 + assign \fus_cu_wr__go_i$91 [2] \wr_pick_rise$962 + assign \fus_cu_wr__go_i$91 [1] \wr_pick_rise$963 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 32 \write_en$964 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + wire width 32 $965 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + cell $sshl $966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_rego + connect \Y $965 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 32 $967 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $968 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$950 + connect \B \wrpick_INT_o_en_o + connect \Y $968 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $970 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $965 + connect \S $968 + connect \Y $967 + end + process $group_347 + assign \write_en$964 32'00000000000000000000000000000000 + assign \write_en$964 $967 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_div0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $820 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $821 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $971 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163422,17 +164064,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$92 connect \B \fus_cu_busy_o$19 - connect \Y $820 + connect \Y $971 end - process $group_306 + process $group_348 assign \wrflag_div0_o_0 1'0 - assign \wrflag_div0_o_0 $820 + assign \wrflag_div0_o_0 $971 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $822 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$973 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $974 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163440,80 +164084,123 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [5] connect \B \wrpick_INT_o_en_o - connect \Y $822 + connect \Y $974 end - process $group_307 - assign \wr_pick$742 1'0 - assign \wr_pick$742 $822 + process $group_349 + assign \wr_pick$973 1'0 + assign \wr_pick$973 $974 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$824 + wire width 1 \wr_pick_dly$976 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$824$next - process $group_308 - assign \wr_pick_dly$824$next \wr_pick_dly$824 - assign \wr_pick_dly$824$next \wr_pick$742 + wire width 1 \wr_pick_dly$976$next + process $group_350 + assign \wr_pick_dly$976$next \wr_pick_dly$976 + assign \wr_pick_dly$976$next \wr_pick$973 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$824$next 1'0 + assign \wr_pick_dly$976$next 1'0 end sync init - update \wr_pick_dly$824 1'0 + update \wr_pick_dly$976 1'0 sync posedge \coresync_clk - update \wr_pick_dly$824 \wr_pick_dly$824$next + update \wr_pick_dly$976 \wr_pick_dly$976$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$825 + wire width 1 \wr_pick_rise$977 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $826 + wire width 1 $978 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $827 + cell $not $979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$824 - connect \Y $826 + connect \A \wr_pick_dly$976 + connect \Y $978 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $828 + wire width 1 $980 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $829 + cell $and $981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$742 - connect \B $826 - connect \Y $828 + connect \A \wr_pick$973 + connect \B $978 + connect \Y $980 end - process $group_309 - assign \wr_pick_rise$825 1'0 - assign \wr_pick_rise$825 $828 + process $group_351 + assign \wr_pick_rise$977 1'0 + assign \wr_pick_rise$977 $980 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$830 + wire width 1 \wr_pick_rise$982 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$831 + wire width 1 \wr_pick_rise$983 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$832 - process $group_310 + wire width 1 \wr_pick_rise$984 + process $group_352 assign \fus_cu_wr__go_i$94 4'0000 - assign \fus_cu_wr__go_i$94 [0] \wr_pick_rise$825 - assign \fus_cu_wr__go_i$94 [1] \wr_pick_rise$830 - assign \fus_cu_wr__go_i$94 [2] \wr_pick_rise$831 - assign \fus_cu_wr__go_i$94 [3] \wr_pick_rise$832 + assign \fus_cu_wr__go_i$94 [0] \wr_pick_rise$977 + assign \fus_cu_wr__go_i$94 [1] \wr_pick_rise$982 + assign \fus_cu_wr__go_i$94 [2] \wr_pick_rise$983 + assign \fus_cu_wr__go_i$94 [3] \wr_pick_rise$984 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 32 \write_en$985 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + wire width 32 $986 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + cell $sshl $987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_rego + connect \Y $986 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 32 $988 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $989 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$973 + connect \B \wrpick_INT_o_en_o + connect \Y $989 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $991 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $986 + connect \S $989 + connect \Y $988 + end + process $group_353 + assign \write_en$985 32'00000000000000000000000000000000 + assign \write_en$985 $988 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_mul0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $833 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $992 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163521,17 +164208,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$95 connect \B \fus_cu_busy_o$22 - connect \Y $833 + connect \Y $992 end - process $group_311 + process $group_354 assign \wrflag_mul0_o_0 1'0 - assign \wrflag_mul0_o_0 $833 + assign \wrflag_mul0_o_0 $992 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $835 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$994 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $995 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163539,80 +164228,123 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [6] connect \B \wrpick_INT_o_en_o - connect \Y $835 + connect \Y $995 end - process $group_312 - assign \wr_pick$747 1'0 - assign \wr_pick$747 $835 + process $group_355 + assign \wr_pick$994 1'0 + assign \wr_pick$994 $995 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$837 + wire width 1 \wr_pick_dly$997 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$837$next - process $group_313 - assign \wr_pick_dly$837$next \wr_pick_dly$837 - assign \wr_pick_dly$837$next \wr_pick$747 + wire width 1 \wr_pick_dly$997$next + process $group_356 + assign \wr_pick_dly$997$next \wr_pick_dly$997 + assign \wr_pick_dly$997$next \wr_pick$994 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$837$next 1'0 + assign \wr_pick_dly$997$next 1'0 end sync init - update \wr_pick_dly$837 1'0 + update \wr_pick_dly$997 1'0 sync posedge \coresync_clk - update \wr_pick_dly$837 \wr_pick_dly$837$next + update \wr_pick_dly$997 \wr_pick_dly$997$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$838 + wire width 1 \wr_pick_rise$998 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $839 + wire width 1 $999 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $840 + cell $not $1000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$837 - connect \Y $839 + connect \A \wr_pick_dly$997 + connect \Y $999 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $841 + wire width 1 $1001 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $842 + cell $and $1002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$747 - connect \B $839 - connect \Y $841 + connect \A \wr_pick$994 + connect \B $999 + connect \Y $1001 end - process $group_314 - assign \wr_pick_rise$838 1'0 - assign \wr_pick_rise$838 $841 + process $group_357 + assign \wr_pick_rise$998 1'0 + assign \wr_pick_rise$998 $1001 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$843 + wire width 1 \wr_pick_rise$1003 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$844 + wire width 1 \wr_pick_rise$1004 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$845 - process $group_315 + wire width 1 \wr_pick_rise$1005 + process $group_358 assign \fus_cu_wr__go_i$97 4'0000 - assign \fus_cu_wr__go_i$97 [0] \wr_pick_rise$838 - assign \fus_cu_wr__go_i$97 [1] \wr_pick_rise$843 - assign \fus_cu_wr__go_i$97 [2] \wr_pick_rise$844 - assign \fus_cu_wr__go_i$97 [3] \wr_pick_rise$845 + assign \fus_cu_wr__go_i$97 [0] \wr_pick_rise$998 + assign \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1003 + assign \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1004 + assign \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1005 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 32 \write_en$1006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + wire width 32 $1007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + cell $sshl $1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_rego + connect \Y $1007 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 32 $1009 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$994 + connect \B \wrpick_INT_o_en_o + connect \Y $1010 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1012 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $1007 + connect \S $1010 + connect \Y $1009 + end + process $group_359 + assign \write_en$1006 32'00000000000000000000000000000000 + assign \write_en$1006 $1009 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_shiftrot0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $846 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $847 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1013 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163620,17 +164352,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$98 connect \B \fus_cu_busy_o$25 - connect \Y $846 + connect \Y $1013 end - process $group_316 + process $group_360 assign \wrflag_shiftrot0_o_0 1'0 - assign \wrflag_shiftrot0_o_0 $846 + assign \wrflag_shiftrot0_o_0 $1013 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $848 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $849 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1015 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1016 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163638,79 +164372,122 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [7] connect \B \wrpick_INT_o_en_o - connect \Y $848 + connect \Y $1016 end - process $group_317 - assign \wr_pick$752 1'0 - assign \wr_pick$752 $848 + process $group_361 + assign \wr_pick$1015 1'0 + assign \wr_pick$1015 $1016 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$850 + wire width 1 \wr_pick_dly$1018 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$850$next - process $group_318 - assign \wr_pick_dly$850$next \wr_pick_dly$850 - assign \wr_pick_dly$850$next \wr_pick$752 + wire width 1 \wr_pick_dly$1018$next + process $group_362 + assign \wr_pick_dly$1018$next \wr_pick_dly$1018 + assign \wr_pick_dly$1018$next \wr_pick$1015 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$850$next 1'0 + assign \wr_pick_dly$1018$next 1'0 end sync init - update \wr_pick_dly$850 1'0 + update \wr_pick_dly$1018 1'0 sync posedge \coresync_clk - update \wr_pick_dly$850 \wr_pick_dly$850$next + update \wr_pick_dly$1018 \wr_pick_dly$1018$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$851 + wire width 1 \wr_pick_rise$1019 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $852 + wire width 1 $1020 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $853 + cell $not $1021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$850 - connect \Y $852 + connect \A \wr_pick_dly$1018 + connect \Y $1020 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $854 + wire width 1 $1022 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $855 + cell $and $1023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$752 - connect \B $852 - connect \Y $854 + connect \A \wr_pick$1015 + connect \B $1020 + connect \Y $1022 end - process $group_319 - assign \wr_pick_rise$851 1'0 - assign \wr_pick_rise$851 $854 + process $group_363 + assign \wr_pick_rise$1019 1'0 + assign \wr_pick_rise$1019 $1022 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$856 + wire width 1 \wr_pick_rise$1024 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$857 - process $group_320 + wire width 1 \wr_pick_rise$1025 + process $group_364 assign \fus_cu_wr__go_i$100 3'000 - assign \fus_cu_wr__go_i$100 [0] \wr_pick_rise$851 - assign \fus_cu_wr__go_i$100 [1] \wr_pick_rise$856 - assign \fus_cu_wr__go_i$100 [2] \wr_pick_rise$857 + assign \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1019 + assign \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1024 + assign \fus_cu_wr__go_i$100 [2] \wr_pick_rise$1025 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 32 \write_en$1026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + wire width 32 $1027 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + cell $sshl $1028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_rego + connect \Y $1027 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 32 $1029 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1030 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1015 + connect \B \wrpick_INT_o_en_o + connect \Y $1030 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1032 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $1027 + connect \S $1030 + connect \Y $1029 + end + process $group_365 + assign \write_en$1026 32'00000000000000000000000000000000 + assign \write_en$1026 $1029 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_ldst0_o_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $858 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $859 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1033 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163718,17 +164495,19 @@ module \core parameter \Y_WIDTH 1 connect \A \o_ok connect \B \fus_cu_busy_o$28 - connect \Y $858 + connect \Y $1033 end - process $group_321 + process $group_366 assign \wrflag_ldst0_o_0 1'0 - assign \wrflag_ldst0_o_0 $858 + assign \wrflag_ldst0_o_0 $1033 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $860 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $861 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1035 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1036 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163736,76 +164515,119 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [8] connect \B \wrpick_INT_o_en_o - connect \Y $860 + connect \Y $1036 end - process $group_322 - assign \wr_pick$757 1'0 - assign \wr_pick$757 $860 + process $group_367 + assign \wr_pick$1035 1'0 + assign \wr_pick$1035 $1036 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$862 + wire width 1 \wr_pick_dly$1038 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$862$next - process $group_323 - assign \wr_pick_dly$862$next \wr_pick_dly$862 - assign \wr_pick_dly$862$next \wr_pick$757 + wire width 1 \wr_pick_dly$1038$next + process $group_368 + assign \wr_pick_dly$1038$next \wr_pick_dly$1038 + assign \wr_pick_dly$1038$next \wr_pick$1035 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$862$next 1'0 + assign \wr_pick_dly$1038$next 1'0 end sync init - update \wr_pick_dly$862 1'0 + update \wr_pick_dly$1038 1'0 sync posedge \coresync_clk - update \wr_pick_dly$862 \wr_pick_dly$862$next + update \wr_pick_dly$1038 \wr_pick_dly$1038$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$863 + wire width 1 \wr_pick_rise$1039 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $864 + wire width 1 $1040 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $865 + cell $not $1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$862 - connect \Y $864 + connect \A \wr_pick_dly$1038 + connect \Y $1040 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $866 + wire width 1 $1042 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $867 + cell $and $1043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$757 - connect \B $864 - connect \Y $866 + connect \A \wr_pick$1035 + connect \B $1040 + connect \Y $1042 end - process $group_324 - assign \wr_pick_rise$863 1'0 - assign \wr_pick_rise$863 $866 + process $group_369 + assign \wr_pick_rise$1039 1'0 + assign \wr_pick_rise$1039 $1042 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$868 - process $group_325 + wire width 1 \wr_pick_rise$1044 + process $group_370 assign \fus_cu_wr__go_i$102 2'00 - assign \fus_cu_wr__go_i$102 [0] \wr_pick_rise$863 - assign \fus_cu_wr__go_i$102 [1] \wr_pick_rise$868 + assign \fus_cu_wr__go_i$102 [0] \wr_pick_rise$1039 + assign \fus_cu_wr__go_i$102 [1] \wr_pick_rise$1044 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 32 \write_en$1045 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + wire width 32 $1046 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129" + cell $sshl $1047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_rego + connect \Y $1046 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 32 $1048 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1049 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1035 + connect \B \wrpick_INT_o_en_o + connect \Y $1049 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1051 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $1046 + connect \S $1049 + connect \Y $1048 + end + process $group_371 + assign \write_en$1045 32'00000000000000000000000000000000 + assign \write_en$1045 $1048 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_ldst0_o_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $869 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $870 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1052 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163813,17 +164635,19 @@ module \core parameter \Y_WIDTH 1 connect \A \ea_ok connect \B \fus_cu_busy_o$28 - connect \Y $869 + connect \Y $1052 end - process $group_326 + process $group_372 assign \wrflag_ldst0_o_1 1'0 - assign \wrflag_ldst0_o_1 $869 + assign \wrflag_ldst0_o_1 $1052 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $871 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $872 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1054 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1055 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -163831,64 +164655,107 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [9] connect \B \wrpick_INT_o_en_o - connect \Y $871 + connect \Y $1055 end - process $group_327 - assign \wr_pick$762 1'0 - assign \wr_pick$762 $871 + process $group_373 + assign \wr_pick$1054 1'0 + assign \wr_pick$1054 $1055 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$873 + wire width 1 \wr_pick_dly$1057 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$873$next - process $group_328 - assign \wr_pick_dly$873$next \wr_pick_dly$873 - assign \wr_pick_dly$873$next \wr_pick$762 + wire width 1 \wr_pick_dly$1057$next + process $group_374 + assign \wr_pick_dly$1057$next \wr_pick_dly$1057 + assign \wr_pick_dly$1057$next \wr_pick$1054 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$873$next 1'0 + assign \wr_pick_dly$1057$next 1'0 end sync init - update \wr_pick_dly$873 1'0 + update \wr_pick_dly$1057 1'0 sync posedge \coresync_clk - update \wr_pick_dly$873 \wr_pick_dly$873$next + update \wr_pick_dly$1057 \wr_pick_dly$1057$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $874 + wire width 1 $1058 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $875 + cell $not $1059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$873 - connect \Y $874 + connect \A \wr_pick_dly$1057 + connect \Y $1058 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $876 + wire width 1 $1060 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $877 + cell $and $1061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$762 - connect \B $874 - connect \Y $876 + connect \A \wr_pick$1054 + connect \B $1058 + connect \Y $1060 end - process $group_329 - assign \wr_pick_rise$868 1'0 - assign \wr_pick_rise$868 $876 + process $group_375 + assign \wr_pick_rise$1044 1'0 + assign \wr_pick_rise$1044 $1060 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 32 \write_en$1062 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:131" + wire width 32 $1063 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:131" + cell $sshl $1064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A 1'1 + connect \B \pdecode2_ea + connect \Y $1063 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 32 $1065 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1066 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1054 + connect \B \wrpick_INT_o_en_o + connect \Y $1066 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1068 + parameter \WIDTH 32 + connect \A 32'00000000000000000000000000000000 + connect \B $1063 + connect \S $1066 + connect \Y $1065 + end + process $group_376 + assign \write_en$1062 32'00000000000000000000000000000000 + assign \write_en$1062 $1065 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $878 + wire width 65 $1069 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $879 + wire width 64 $1070 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $880 + cell $or $1071 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -163896,12 +164763,12 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o connect \B \fus_dest1_o$103 - connect \Y $879 + connect \Y $1070 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $881 + wire width 64 $1072 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $882 + cell $or $1073 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -163909,38 +164776,38 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$105 connect \B \fus_dest1_o$106 - connect \Y $881 + connect \Y $1072 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $883 + wire width 64 $1074 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $884 + cell $or $1075 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest1_o$104 - connect \B $881 - connect \Y $883 + connect \B $1072 + connect \Y $1074 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $885 + wire width 64 $1076 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $886 + cell $or $1077 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $879 - connect \B $883 - connect \Y $885 + connect \A $1070 + connect \B $1074 + connect \Y $1076 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $887 + wire width 64 $1078 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $888 + cell $or $1079 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -163948,12 +164815,12 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$107 connect \B \fus_dest1_o$108 - connect \Y $887 + connect \Y $1078 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 65 $889 + wire width 65 $1080 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $890 + cell $or $1081 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \B_SIGNED 0 @@ -163961,59 +164828,181 @@ module \core parameter \Y_WIDTH 65 connect \A { \o_ok \fus_o } connect \B { \ea_ok \fus_ea } - connect \Y $889 + connect \Y $1080 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $891 + wire width 65 $1082 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $892 + cell $or $1083 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 connect \A \fus_dest1_o$109 - connect \B $889 - connect \Y $891 + connect \B $1080 + connect \Y $1082 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $893 + wire width 65 $1084 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $894 + cell $or $1085 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $887 - connect \B $891 - connect \Y $893 + connect \A $1078 + connect \B $1082 + connect \Y $1084 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $895 + wire width 65 $1086 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $896 + cell $or $1087 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $885 - connect \B $893 - connect \Y $895 + connect \A $1076 + connect \B $1084 + connect \Y $1086 end - connect $878 $895 - process $group_330 + connect $1069 $1086 + process $group_377 assign \int_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \int_data_i $878 [63:0] + assign \int_data_i $1069 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 32 $1088 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \write_en$879 + connect \B \write_en$899 + connect \Y $1088 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 32 $1090 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \write_en$941 + connect \B \write_en$964 + connect \Y $1090 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 32 $1092 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \write_en$921 + connect \B $1090 + connect \Y $1092 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 32 $1094 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $1088 + connect \B $1092 + connect \Y $1094 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 32 $1096 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \write_en$985 + connect \B \write_en$1006 + connect \Y $1096 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 32 $1098 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \write_en$1045 + connect \B \write_en$1062 + connect \Y $1098 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 32 $1100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \write_en$1026 + connect \B $1098 + connect \Y $1100 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 32 $1102 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $1096 + connect \B $1100 + connect \Y $1102 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 32 $1104 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $1094 + connect \B $1102 + connect \Y $1104 + end + process $group_378 + assign \int_wen 32'00000000000000000000000000000000 + assign \int_wen $1104 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_cr0_full_cr_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $897 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $898 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164021,17 +165010,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_full_cr_ok connect \B \fus_cu_busy_o$4 - connect \Y $897 + connect \Y $1106 end - process $group_331 + process $group_379 assign \wrflag_cr0_full_cr_1 1'0 - assign \wrflag_cr0_full_cr_1 $897 + assign \wrflag_cr0_full_cr_1 $1106 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $899 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $900 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164039,19 +165028,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$81 [1] connect \B \fu_enable [1] - connect \Y $899 + connect \Y $1108 end - process $group_332 + process $group_380 assign \wrpick_CR_full_cr_i 1'0 - assign \wrpick_CR_full_cr_i $899 + assign \wrpick_CR_full_cr_i $1108 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$901 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $902 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $903 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164059,92 +165048,104 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_full_cr_o connect \B \wrpick_CR_full_cr_en_o - connect \Y $902 + connect \Y $1111 end - process $group_333 - assign \wr_pick$901 1'0 - assign \wr_pick$901 $902 + process $group_381 + assign \wr_pick$1110 1'0 + assign \wr_pick$1110 $1111 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$904 + wire width 1 \wr_pick_dly$1113 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$904$next - process $group_334 - assign \wr_pick_dly$904$next \wr_pick_dly$904 - assign \wr_pick_dly$904$next \wr_pick$901 + wire width 1 \wr_pick_dly$1113$next + process $group_382 + assign \wr_pick_dly$1113$next \wr_pick_dly$1113 + assign \wr_pick_dly$1113$next \wr_pick$1110 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$904$next 1'0 + assign \wr_pick_dly$1113$next 1'0 end sync init - update \wr_pick_dly$904 1'0 + update \wr_pick_dly$1113 1'0 sync posedge \coresync_clk - update \wr_pick_dly$904 \wr_pick_dly$904$next + update \wr_pick_dly$1113 \wr_pick_dly$1113$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $905 + wire width 1 $1114 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $906 + cell $not $1115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$904 - connect \Y $905 + connect \A \wr_pick_dly$1113 + connect \Y $1114 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $907 + wire width 1 $1116 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $908 + cell $and $1117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$901 - connect \B $905 - connect \Y $907 + connect \A \wr_pick$1110 + connect \B $1114 + connect \Y $1116 end - process $group_335 - assign \wr_pick_rise$777 1'0 - assign \wr_pick_rise$777 $907 + process $group_383 + assign \wr_pick_rise$897 1'0 + assign \wr_pick_rise$897 $1116 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $909 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $910 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 8 \write_en$1118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 8 $1119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$901 + connect \A \wr_pick$1110 connect \B \wrpick_CR_full_cr_en_o - connect \Y $909 + connect \Y $1120 end - process $group_336 - assign \cr_full_wr__wen 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $909 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \cr_full_wr__wen 8'11111111 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1122 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B 8'11111111 + connect \S $1120 + connect \Y $1119 + end + process $group_384 + assign \write_en$1118 8'00000000 + assign \write_en$1118 $1119 sync init end - process $group_337 + process $group_385 assign \cr_full_wr__data_i 32'00000000000000000000000000000000 assign \cr_full_wr__data_i \fus_dest2_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + process $group_386 + assign \cr_full_wr__wen 8'00000000 + assign \cr_full_wr__wen \write_en$1118 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_alu0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $911 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $912 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164152,17 +165153,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok connect \B \fus_cu_busy_o - connect \Y $911 + connect \Y $1123 end - process $group_338 + process $group_387 assign \wrflag_alu0_cr_a_1 1'0 - assign \wrflag_alu0_cr_a_1 $911 + assign \wrflag_alu0_cr_a_1 $1123 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $913 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $914 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164170,12 +165171,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [1] connect \B \fu_enable [0] - connect \Y $913 + connect \Y $1125 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $915 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $916 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164183,12 +165184,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$81 [2] connect \B \fu_enable [1] - connect \Y $915 + connect \Y $1127 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $917 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164196,12 +165197,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$87 [1] connect \B \fu_enable [4] - connect \Y $917 + connect \Y $1129 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $919 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $920 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164209,12 +165210,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [1] connect \B \fu_enable [6] - connect \Y $919 + connect \Y $1131 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $921 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164222,12 +165223,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [1] connect \B \fu_enable [7] - connect \Y $921 + connect \Y $1133 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $923 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164235,24 +165236,24 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [1] connect \B \fu_enable [8] - connect \Y $923 + connect \Y $1135 end - process $group_339 + process $group_388 assign \wrpick_CR_cr_a_i 6'000000 - assign \wrpick_CR_cr_a_i [0] $913 - assign \wrpick_CR_cr_a_i [1] $915 - assign \wrpick_CR_cr_a_i [2] $917 - assign \wrpick_CR_cr_a_i [3] $919 - assign \wrpick_CR_cr_a_i [4] $921 - assign \wrpick_CR_cr_a_i [5] $923 + assign \wrpick_CR_cr_a_i [0] $1125 + assign \wrpick_CR_cr_a_i [1] $1127 + assign \wrpick_CR_cr_a_i [2] $1129 + assign \wrpick_CR_cr_a_i [3] $1131 + assign \wrpick_CR_cr_a_i [4] $1133 + assign \wrpick_CR_cr_a_i [5] $1135 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$925 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $926 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $927 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164260,77 +165261,64 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [0] connect \B \wrpick_CR_cr_a_en_o - connect \Y $926 + connect \Y $1138 end - process $group_340 - assign \wr_pick$925 1'0 - assign \wr_pick$925 $926 + process $group_389 + assign \wr_pick$1137 1'0 + assign \wr_pick$1137 $1138 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$928 + wire width 1 \wr_pick_dly$1140 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$928$next - process $group_341 - assign \wr_pick_dly$928$next \wr_pick_dly$928 - assign \wr_pick_dly$928$next \wr_pick$925 + wire width 1 \wr_pick_dly$1140$next + process $group_390 + assign \wr_pick_dly$1140$next \wr_pick_dly$1140 + assign \wr_pick_dly$1140$next \wr_pick$1137 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$928$next 1'0 + assign \wr_pick_dly$1140$next 1'0 end sync init - update \wr_pick_dly$928 1'0 + update \wr_pick_dly$1140 1'0 sync posedge \coresync_clk - update \wr_pick_dly$928 \wr_pick_dly$928$next + update \wr_pick_dly$1140 \wr_pick_dly$1140$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $929 + wire width 1 $1141 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $930 + cell $not $1142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$928 - connect \Y $929 + connect \A \wr_pick_dly$1140 + connect \Y $1141 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $931 + wire width 1 $1143 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $932 + cell $and $1144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$925 - connect \B $929 - connect \Y $931 + connect \A \wr_pick$1137 + connect \B $1141 + connect \Y $1143 end - process $group_342 - assign \wr_pick_rise$714 1'0 - assign \wr_pick_rise$714 $931 + process $group_391 + assign \wr_pick_rise$875 1'0 + assign \wr_pick_rise$875 $1143 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $933 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$925 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $933 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $935 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 16 \write_en$1145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 4 $936 + wire width 4 $1146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sub $937 + cell $sub $1147 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -164338,219 +165326,140 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \pdecode2_cr_out - connect \Y $936 + connect \Y $1146 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $938 + wire width 16 $1148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sshl $939 + cell $sshl $1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $936 - connect \Y $938 + connect \B $1146 + connect \Y $1148 end - connect $935 $938 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$940 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $941 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 16 $1150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$940 + connect \A \wr_pick$1137 connect \B \wrpick_CR_cr_a_en_o - connect \Y $941 + connect \Y $1151 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $943 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 4 $944 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sub $945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_out - connect \Y $944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1153 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $1148 + connect \S $1151 + connect \Y $1150 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $946 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sshl $947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $944 - connect \Y $946 + process $group_392 + assign \write_en$1145 16'0000000000000000 + assign \write_en$1145 $1150 + sync init end - connect $943 $946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" + wire width 1 \wrflag_cr0_cr_a_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$948 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $949 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $950 + wire width 1 $1154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$948 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $949 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $951 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 4 $952 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sub $953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_out - connect \Y $952 + connect \A \fus_cr_a_ok$110 + connect \B \fus_cu_busy_o$4 + connect \Y $1154 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $954 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sshl $955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $952 - connect \Y $954 + process $group_393 + assign \wrflag_cr0_cr_a_2 1'0 + assign \wrflag_cr0_cr_a_2 $1154 + sync init end - connect $951 $954 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$956 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $957 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $958 + wire width 1 \wr_pick$1156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$956 + connect \A \wrpick_CR_cr_a_o [1] connect \B \wrpick_CR_cr_a_en_o - connect \Y $957 + connect \Y $1157 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $959 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 4 $960 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sub $961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_out - connect \Y $960 + process $group_394 + assign \wr_pick$1156 1'0 + assign \wr_pick$1156 $1157 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $962 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sshl $963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $960 - connect \Y $962 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1159 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1159$next + process $group_395 + assign \wr_pick_dly$1159$next \wr_pick_dly$1159 + assign \wr_pick_dly$1159$next \wr_pick$1156 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1159$next 1'0 + end + sync init + update \wr_pick_dly$1159 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1159 \wr_pick_dly$1159$next end - connect $959 $962 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$964 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $965 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $966 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1160 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$964 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $965 + connect \A \wr_pick_dly$1159 + connect \Y $1160 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $967 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 4 $968 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sub $969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_out - connect \Y $968 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $970 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sshl $971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $968 - connect \Y $970 - end - connect $967 $970 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$972 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $973 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $974 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1162 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$972 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $973 + connect \A \wr_pick$1156 + connect \B $1160 + connect \Y $1162 end + process $group_396 + assign \wr_pick_rise$898 1'0 + assign \wr_pick_rise$898 $1162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 16 \write_en$1164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $975 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 4 $976 + wire width 4 $1165 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sub $977 + cell $sub $1166 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -164558,151 +165467,55 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \pdecode2_cr_out - connect \Y $976 + connect \Y $1165 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $978 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sshl $979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $976 - connect \Y $978 - end - connect $975 $978 - process $group_343 - assign \cr_wen 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $933 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \cr_wen $935 [7:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $941 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \cr_wen $943 [7:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $949 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \cr_wen $951 [7:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $957 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \cr_wen $959 [7:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $965 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \cr_wen $967 [7:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $973 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \cr_wen $975 [7:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" - wire width 1 \wrflag_cr0_cr_a_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $980 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$110 - connect \B \fus_cu_busy_o$4 - connect \Y $980 - end - process $group_344 - assign \wrflag_cr0_cr_a_2 1'0 - assign \wrflag_cr0_cr_a_2 $980 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $982 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $983 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [1] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $982 - end - process $group_345 - assign \wr_pick$940 1'0 - assign \wr_pick$940 $982 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$984 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$984$next - process $group_346 - assign \wr_pick_dly$984$next \wr_pick_dly$984 - assign \wr_pick_dly$984$next \wr_pick$940 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$984$next 1'0 - end - sync init - update \wr_pick_dly$984 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$984 \wr_pick_dly$984$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $985 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $986 + wire width 16 $1167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + cell $sshl $1168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$984 - connect \Y $985 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $1165 + connect \Y $1167 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $987 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $988 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 16 $1169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$940 - connect \B $985 - connect \Y $987 + connect \A \wr_pick$1156 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1170 end - process $group_347 - assign \wr_pick_rise$778 1'0 - assign \wr_pick_rise$778 $987 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1172 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $1167 + connect \S $1170 + connect \Y $1169 + end + process $group_397 + assign \write_en$1164 16'0000000000000000 + assign \write_en$1164 $1169 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_logical0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $989 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $990 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164710,17 +165523,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$111 connect \B \fus_cu_busy_o$13 - connect \Y $989 + connect \Y $1173 end - process $group_348 + process $group_398 assign \wrflag_logical0_cr_a_1 1'0 - assign \wrflag_logical0_cr_a_1 $989 + assign \wrflag_logical0_cr_a_1 $1173 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $991 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $992 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164728,64 +165543,120 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [2] connect \B \wrpick_CR_cr_a_en_o - connect \Y $991 + connect \Y $1176 end - process $group_349 - assign \wr_pick$948 1'0 - assign \wr_pick$948 $991 + process $group_399 + assign \wr_pick$1175 1'0 + assign \wr_pick$1175 $1176 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$993 + wire width 1 \wr_pick_dly$1178 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$993$next - process $group_350 - assign \wr_pick_dly$993$next \wr_pick_dly$993 - assign \wr_pick_dly$993$next \wr_pick$948 + wire width 1 \wr_pick_dly$1178$next + process $group_400 + assign \wr_pick_dly$1178$next \wr_pick_dly$1178 + assign \wr_pick_dly$1178$next \wr_pick$1175 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$993$next 1'0 + assign \wr_pick_dly$1178$next 1'0 end sync init - update \wr_pick_dly$993 1'0 + update \wr_pick_dly$1178 1'0 sync posedge \coresync_clk - update \wr_pick_dly$993 \wr_pick_dly$993$next + update \wr_pick_dly$1178 \wr_pick_dly$1178$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $994 + wire width 1 $1179 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $995 + cell $not $1180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$993 - connect \Y $994 + connect \A \wr_pick_dly$1178 + connect \Y $1179 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $996 + wire width 1 $1181 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $997 + cell $and $1182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$948 - connect \B $994 - connect \Y $996 + connect \A \wr_pick$1175 + connect \B $1179 + connect \Y $1181 end - process $group_351 - assign \wr_pick_rise$803 1'0 - assign \wr_pick_rise$803 $996 + process $group_401 + assign \wr_pick_rise$939 1'0 + assign \wr_pick_rise$939 $1181 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 16 \write_en$1183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + wire width 4 $1184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + cell $sub $1185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \pdecode2_cr_out + connect \Y $1184 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + wire width 16 $1186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + cell $sshl $1187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $1184 + connect \Y $1186 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 16 $1188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1175 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1189 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1191 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $1186 + connect \S $1189 + connect \Y $1188 + end + process $group_402 + assign \write_en$1183 16'0000000000000000 + assign \write_en$1183 $1188 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_div0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $998 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $999 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164793,17 +165664,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$112 connect \B \fus_cu_busy_o$19 - connect \Y $998 + connect \Y $1192 end - process $group_352 + process $group_403 assign \wrflag_div0_cr_a_1 1'0 - assign \wrflag_div0_cr_a_1 $998 + assign \wrflag_div0_cr_a_1 $1192 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164811,64 +165684,120 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [3] connect \B \wrpick_CR_cr_a_en_o - connect \Y $1000 + connect \Y $1195 end - process $group_353 - assign \wr_pick$956 1'0 - assign \wr_pick$956 $1000 + process $group_404 + assign \wr_pick$1194 1'0 + assign \wr_pick$1194 $1195 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1002 + wire width 1 \wr_pick_dly$1197 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1002$next - process $group_354 - assign \wr_pick_dly$1002$next \wr_pick_dly$1002 - assign \wr_pick_dly$1002$next \wr_pick$956 + wire width 1 \wr_pick_dly$1197$next + process $group_405 + assign \wr_pick_dly$1197$next \wr_pick_dly$1197 + assign \wr_pick_dly$1197$next \wr_pick$1194 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1002$next 1'0 + assign \wr_pick_dly$1197$next 1'0 end sync init - update \wr_pick_dly$1002 1'0 + update \wr_pick_dly$1197 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1002 \wr_pick_dly$1002$next + update \wr_pick_dly$1197 \wr_pick_dly$1197$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1003 + wire width 1 $1198 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1004 + cell $not $1199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1002 - connect \Y $1003 + connect \A \wr_pick_dly$1197 + connect \Y $1198 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1005 + wire width 1 $1200 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1006 + cell $and $1201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$956 - connect \B $1003 - connect \Y $1005 + connect \A \wr_pick$1194 + connect \B $1198 + connect \Y $1200 end - process $group_355 - assign \wr_pick_rise$830 1'0 - assign \wr_pick_rise$830 $1005 + process $group_406 + assign \wr_pick_rise$982 1'0 + assign \wr_pick_rise$982 $1200 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 16 \write_en$1202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + wire width 4 $1203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + cell $sub $1204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \pdecode2_cr_out + connect \Y $1203 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + wire width 16 $1205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + cell $sshl $1206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $1203 + connect \Y $1205 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 16 $1207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1194 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1208 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1210 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $1205 + connect \S $1208 + connect \Y $1207 + end + process $group_407 + assign \write_en$1202 16'0000000000000000 + assign \write_en$1202 $1207 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_mul0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1007 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1008 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164876,17 +165805,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$113 connect \B \fus_cu_busy_o$22 - connect \Y $1007 + connect \Y $1211 end - process $group_356 + process $group_408 assign \wrflag_mul0_cr_a_1 1'0 - assign \wrflag_mul0_cr_a_1 $1007 + assign \wrflag_mul0_cr_a_1 $1211 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1009 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164894,64 +165825,120 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [4] connect \B \wrpick_CR_cr_a_en_o - connect \Y $1009 + connect \Y $1214 end - process $group_357 - assign \wr_pick$964 1'0 - assign \wr_pick$964 $1009 + process $group_409 + assign \wr_pick$1213 1'0 + assign \wr_pick$1213 $1214 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1011 + wire width 1 \wr_pick_dly$1216 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1011$next - process $group_358 - assign \wr_pick_dly$1011$next \wr_pick_dly$1011 - assign \wr_pick_dly$1011$next \wr_pick$964 + wire width 1 \wr_pick_dly$1216$next + process $group_410 + assign \wr_pick_dly$1216$next \wr_pick_dly$1216 + assign \wr_pick_dly$1216$next \wr_pick$1213 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1011$next 1'0 + assign \wr_pick_dly$1216$next 1'0 end sync init - update \wr_pick_dly$1011 1'0 + update \wr_pick_dly$1216 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1011 \wr_pick_dly$1011$next + update \wr_pick_dly$1216 \wr_pick_dly$1216$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1012 + wire width 1 $1217 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1013 + cell $not $1218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1011 - connect \Y $1012 + connect \A \wr_pick_dly$1216 + connect \Y $1217 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1014 + wire width 1 $1219 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1015 + cell $and $1220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$964 - connect \B $1012 - connect \Y $1014 + connect \A \wr_pick$1213 + connect \B $1217 + connect \Y $1219 end - process $group_359 - assign \wr_pick_rise$843 1'0 - assign \wr_pick_rise$843 $1014 + process $group_411 + assign \wr_pick_rise$1003 1'0 + assign \wr_pick_rise$1003 $1219 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 16 \write_en$1221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + wire width 4 $1222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + cell $sub $1223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \pdecode2_cr_out + connect \Y $1222 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + wire width 16 $1224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + cell $sshl $1225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $1222 + connect \Y $1224 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 16 $1226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1213 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1227 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1229 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $1224 + connect \S $1227 + connect \Y $1226 + end + process $group_412 + assign \write_en$1221 16'0000000000000000 + assign \write_en$1221 $1226 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_shiftrot0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1016 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1017 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164959,17 +165946,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$114 connect \B \fus_cu_busy_o$25 - connect \Y $1016 + connect \Y $1230 end - process $group_360 + process $group_413 assign \wrflag_shiftrot0_cr_a_1 1'0 - assign \wrflag_shiftrot0_cr_a_1 $1016 + assign \wrflag_shiftrot0_cr_a_1 $1230 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1018 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1019 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1232 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -164977,62 +165966,118 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [5] connect \B \wrpick_CR_cr_a_en_o - connect \Y $1018 + connect \Y $1233 end - process $group_361 - assign \wr_pick$972 1'0 - assign \wr_pick$972 $1018 + process $group_414 + assign \wr_pick$1232 1'0 + assign \wr_pick$1232 $1233 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1020 + wire width 1 \wr_pick_dly$1235 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1020$next - process $group_362 - assign \wr_pick_dly$1020$next \wr_pick_dly$1020 - assign \wr_pick_dly$1020$next \wr_pick$972 + wire width 1 \wr_pick_dly$1235$next + process $group_415 + assign \wr_pick_dly$1235$next \wr_pick_dly$1235 + assign \wr_pick_dly$1235$next \wr_pick$1232 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1020$next 1'0 + assign \wr_pick_dly$1235$next 1'0 end sync init - update \wr_pick_dly$1020 1'0 + update \wr_pick_dly$1235 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1020 \wr_pick_dly$1020$next + update \wr_pick_dly$1235 \wr_pick_dly$1235$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1021 + wire width 1 $1236 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1022 + cell $not $1237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1020 - connect \Y $1021 + connect \A \wr_pick_dly$1235 + connect \Y $1236 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1023 + wire width 1 $1238 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1024 + cell $and $1239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$972 - connect \B $1021 - connect \Y $1023 + connect \A \wr_pick$1232 + connect \B $1236 + connect \Y $1238 end - process $group_363 - assign \wr_pick_rise$856 1'0 - assign \wr_pick_rise$856 $1023 + process $group_416 + assign \wr_pick_rise$1024 1'0 + assign \wr_pick_rise$1024 $1238 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 16 \write_en$1240 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + wire width 4 $1241 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + cell $sub $1242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \pdecode2_cr_out + connect \Y $1241 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + wire width 16 $1243 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" + cell $sshl $1244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $1241 + connect \Y $1243 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 16 $1245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1246 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1232 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1246 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1248 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $1243 + connect \S $1246 + connect \Y $1245 + end + process $group_417 + assign \write_en$1240 16'0000000000000000 + assign \write_en$1240 $1245 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $1025 + wire width 4 $1249 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1026 + cell $or $1250 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -165040,25 +166085,25 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest3_o connect \B \fus_dest2_o$116 - connect \Y $1025 + connect \Y $1249 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $1027 + wire width 4 $1251 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1028 + cell $or $1252 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_dest2_o$115 - connect \B $1025 - connect \Y $1027 + connect \B $1249 + connect \Y $1251 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $1029 + wire width 4 $1253 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1030 + cell $or $1254 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -165066,45 +166111,118 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest2_o$118 connect \B \fus_dest2_o$119 - connect \Y $1029 + connect \Y $1253 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $1031 + wire width 4 $1255 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1032 + cell $or $1256 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_dest2_o$117 - connect \B $1029 - connect \Y $1031 + connect \B $1253 + connect \Y $1255 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $1033 + wire width 4 $1257 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1034 + cell $or $1258 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $1027 - connect \B $1031 - connect \Y $1033 + connect \A $1251 + connect \B $1255 + connect \Y $1257 + end + process $group_418 + assign \cr_data_i 4'0000 + assign \cr_data_i $1257 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 16 $1259 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 16 $1260 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \write_en$1164 + connect \B \write_en$1183 + connect \Y $1260 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 16 $1262 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \write_en$1145 + connect \B $1260 + connect \Y $1262 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 16 $1264 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \write_en$1221 + connect \B \write_en$1240 + connect \Y $1264 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 16 $1266 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \write_en$1202 + connect \B $1264 + connect \Y $1266 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 16 $1268 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A $1262 + connect \B $1266 + connect \Y $1268 end - process $group_364 - assign \cr_data_i 4'0000 - assign \cr_data_i $1033 + connect $1259 $1268 + process $group_419 + assign \cr_wen 8'00000000 + assign \cr_wen $1259 [7:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_alu0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1035 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1036 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165112,17 +166230,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok connect \B \fus_cu_busy_o - connect \Y $1035 + connect \Y $1270 end - process $group_365 + process $group_420 assign \wrflag_alu0_xer_ca_2 1'0 - assign \wrflag_alu0_xer_ca_2 $1035 + assign \wrflag_alu0_xer_ca_2 $1270 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1037 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1272 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165130,12 +166248,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [2] connect \B \fu_enable [0] - connect \Y $1037 + connect \Y $1272 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1039 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1040 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165143,12 +166261,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$87 [2] connect \B \fu_enable [4] - connect \Y $1039 + connect \Y $1274 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1041 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1042 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165156,12 +166274,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$90 [5] connect \B \fu_enable [5] - connect \Y $1041 + connect \Y $1276 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1043 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1044 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165169,22 +166287,22 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [2] connect \B \fu_enable [8] - connect \Y $1043 + connect \Y $1278 end - process $group_366 + process $group_421 assign \wrpick_XER_xer_ca_i 4'0000 - assign \wrpick_XER_xer_ca_i [0] $1037 - assign \wrpick_XER_xer_ca_i [1] $1039 - assign \wrpick_XER_xer_ca_i [2] $1041 - assign \wrpick_XER_xer_ca_i [3] $1043 + assign \wrpick_XER_xer_ca_i [0] $1272 + assign \wrpick_XER_xer_ca_i [1] $1274 + assign \wrpick_XER_xer_ca_i [2] $1276 + assign \wrpick_XER_xer_ca_i [3] $1278 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1045 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1046 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1047 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1281 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165192,150 +166310,94 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [0] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1046 + connect \Y $1281 end - process $group_367 - assign \wr_pick$1045 1'0 - assign \wr_pick$1045 $1046 + process $group_422 + assign \wr_pick$1280 1'0 + assign \wr_pick$1280 $1281 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1048 + wire width 1 \wr_pick_dly$1283 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1048$next - process $group_368 - assign \wr_pick_dly$1048$next \wr_pick_dly$1048 - assign \wr_pick_dly$1048$next \wr_pick$1045 + wire width 1 \wr_pick_dly$1283$next + process $group_423 + assign \wr_pick_dly$1283$next \wr_pick_dly$1283 + assign \wr_pick_dly$1283$next \wr_pick$1280 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1048$next 1'0 + assign \wr_pick_dly$1283$next 1'0 end sync init - update \wr_pick_dly$1048 1'0 + update \wr_pick_dly$1283 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1048 \wr_pick_dly$1048$next + update \wr_pick_dly$1283 \wr_pick_dly$1283$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1049 + wire width 1 $1284 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1050 + cell $not $1285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1048 - connect \Y $1049 + connect \A \wr_pick_dly$1283 + connect \Y $1284 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1051 + wire width 1 $1286 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1052 + cell $and $1287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1045 - connect \B $1049 - connect \Y $1051 + connect \A \wr_pick$1280 + connect \B $1284 + connect \Y $1286 end - process $group_369 - assign \wr_pick_rise$715 1'0 - assign \wr_pick_rise$715 $1051 + process $group_424 + assign \wr_pick_rise$876 1'0 + assign \wr_pick_rise$876 $1286 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1053 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1045 - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1053 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1055 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1056 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1055 - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1056 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1058 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1059 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1060 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 2 \write_en$1288 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 2 $1289 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1058 + connect \A \wr_pick$1280 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1059 + connect \Y $1290 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1061 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1062 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1061 - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1062 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1292 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S $1290 + connect \Y $1289 end - process $group_370 - assign \xer_wen 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1053 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \xer_wen 3'010 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1056 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \xer_wen 3'010 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1059 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \xer_wen 3'010 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1062 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \xer_wen 3'010 - end + process $group_425 + assign \write_en$1288 2'00 + assign \write_en$1288 $1289 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_logical0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1064 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1065 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1293 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165343,17 +166405,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$120 connect \B \fus_cu_busy_o$13 - connect \Y $1064 + connect \Y $1293 end - process $group_371 + process $group_426 assign \wrflag_logical0_xer_ca_2 1'0 - assign \wrflag_logical0_xer_ca_2 $1064 + assign \wrflag_logical0_xer_ca_2 $1293 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1066 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1067 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1295 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165361,64 +166425,94 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [1] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1066 + connect \Y $1296 end - process $group_372 - assign \wr_pick$1055 1'0 - assign \wr_pick$1055 $1066 + process $group_427 + assign \wr_pick$1295 1'0 + assign \wr_pick$1295 $1296 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1068 + wire width 1 \wr_pick_dly$1298 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1068$next - process $group_373 - assign \wr_pick_dly$1068$next \wr_pick_dly$1068 - assign \wr_pick_dly$1068$next \wr_pick$1055 + wire width 1 \wr_pick_dly$1298$next + process $group_428 + assign \wr_pick_dly$1298$next \wr_pick_dly$1298 + assign \wr_pick_dly$1298$next \wr_pick$1295 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1068$next 1'0 + assign \wr_pick_dly$1298$next 1'0 end sync init - update \wr_pick_dly$1068 1'0 + update \wr_pick_dly$1298 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1068 \wr_pick_dly$1068$next + update \wr_pick_dly$1298 \wr_pick_dly$1298$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1069 + wire width 1 $1299 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1070 + cell $not $1300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1068 - connect \Y $1069 + connect \A \wr_pick_dly$1298 + connect \Y $1299 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1071 + wire width 1 $1301 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1072 + cell $and $1302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1055 - connect \B $1069 - connect \Y $1071 + connect \A \wr_pick$1295 + connect \B $1299 + connect \Y $1301 end - process $group_374 - assign \wr_pick_rise$804 1'0 - assign \wr_pick_rise$804 $1071 + process $group_429 + assign \wr_pick_rise$940 1'0 + assign \wr_pick_rise$940 $1301 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 2 \write_en$1303 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 2 $1304 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1295 + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $1305 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1307 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S $1305 + connect \Y $1304 + end + process $group_430 + assign \write_en$1303 2'00 + assign \write_en$1303 $1304 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_spr0_xer_ca_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1073 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1074 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165426,17 +166520,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$121 connect \B \fus_cu_busy_o$16 - connect \Y $1073 + connect \Y $1308 end - process $group_375 + process $group_431 assign \wrflag_spr0_xer_ca_5 1'0 - assign \wrflag_spr0_xer_ca_5 $1073 + assign \wrflag_spr0_xer_ca_5 $1308 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1075 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1076 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165444,64 +166540,94 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [2] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1075 + connect \Y $1311 end - process $group_376 - assign \wr_pick$1058 1'0 - assign \wr_pick$1058 $1075 + process $group_432 + assign \wr_pick$1310 1'0 + assign \wr_pick$1310 $1311 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1077 + wire width 1 \wr_pick_dly$1313 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1077$next - process $group_377 - assign \wr_pick_dly$1077$next \wr_pick_dly$1077 - assign \wr_pick_dly$1077$next \wr_pick$1058 + wire width 1 \wr_pick_dly$1313$next + process $group_433 + assign \wr_pick_dly$1313$next \wr_pick_dly$1313 + assign \wr_pick_dly$1313$next \wr_pick$1310 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1077$next 1'0 + assign \wr_pick_dly$1313$next 1'0 end sync init - update \wr_pick_dly$1077 1'0 + update \wr_pick_dly$1313 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1077 \wr_pick_dly$1077$next + update \wr_pick_dly$1313 \wr_pick_dly$1313$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1078 + wire width 1 $1314 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1079 + cell $not $1315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1077 - connect \Y $1078 + connect \A \wr_pick_dly$1313 + connect \Y $1314 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1080 + wire width 1 $1316 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1081 + cell $and $1317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1058 - connect \B $1078 - connect \Y $1080 + connect \A \wr_pick$1310 + connect \B $1314 + connect \Y $1316 end - process $group_378 - assign \wr_pick_rise$815 1'0 - assign \wr_pick_rise$815 $1080 + process $group_434 + assign \wr_pick_rise$959 1'0 + assign \wr_pick_rise$959 $1316 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 2 \write_en$1318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 2 $1319 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1310 + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $1320 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1322 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S $1320 + connect \Y $1319 + end + process $group_435 + assign \write_en$1318 2'00 + assign \write_en$1318 $1319 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_shiftrot0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1082 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1083 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1323 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165509,17 +166635,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$122 connect \B \fus_cu_busy_o$25 - connect \Y $1082 + connect \Y $1323 end - process $group_379 + process $group_436 assign \wrflag_shiftrot0_xer_ca_2 1'0 - assign \wrflag_shiftrot0_xer_ca_2 $1082 + assign \wrflag_shiftrot0_xer_ca_2 $1323 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1084 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1085 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1325 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165527,62 +166655,92 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [3] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1084 + connect \Y $1326 end - process $group_380 - assign \wr_pick$1061 1'0 - assign \wr_pick$1061 $1084 + process $group_437 + assign \wr_pick$1325 1'0 + assign \wr_pick$1325 $1326 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1086 + wire width 1 \wr_pick_dly$1328 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1086$next - process $group_381 - assign \wr_pick_dly$1086$next \wr_pick_dly$1086 - assign \wr_pick_dly$1086$next \wr_pick$1061 + wire width 1 \wr_pick_dly$1328$next + process $group_438 + assign \wr_pick_dly$1328$next \wr_pick_dly$1328 + assign \wr_pick_dly$1328$next \wr_pick$1325 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1086$next 1'0 + assign \wr_pick_dly$1328$next 1'0 end sync init - update \wr_pick_dly$1086 1'0 + update \wr_pick_dly$1328 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1086 \wr_pick_dly$1086$next + update \wr_pick_dly$1328 \wr_pick_dly$1328$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1087 + wire width 1 $1329 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1088 + cell $not $1330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1086 - connect \Y $1087 + connect \A \wr_pick_dly$1328 + connect \Y $1329 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1089 + wire width 1 $1331 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1090 + cell $and $1332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1061 - connect \B $1087 - connect \Y $1089 + connect \A \wr_pick$1325 + connect \B $1329 + connect \Y $1331 end - process $group_382 - assign \wr_pick_rise$857 1'0 - assign \wr_pick_rise$857 $1089 + process $group_439 + assign \wr_pick_rise$1025 1'0 + assign \wr_pick_rise$1025 $1331 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 2 \write_en$1333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 2 $1334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1325 + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $1335 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1337 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S $1335 + connect \Y $1334 + end + process $group_440 + assign \write_en$1333 2'00 + assign \write_en$1333 $1334 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1091 + wire width 2 $1338 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1092 + cell $or $1339 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -165590,12 +166748,12 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest3_o$123 connect \B \fus_dest3_o$124 - connect \Y $1091 + connect \Y $1338 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1093 + wire width 2 $1340 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1094 + cell $or $1341 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -165603,32 +166761,86 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest6_o connect \B \fus_dest3_o$125 - connect \Y $1093 + connect \Y $1340 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $1095 + wire width 2 $1342 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1096 + cell $or $1343 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $1091 - connect \B $1093 - connect \Y $1095 + connect \A $1338 + connect \B $1340 + connect \Y $1342 end - process $group_383 + process $group_441 assign \xer_data_i 2'00 - assign \xer_data_i $1095 + assign \xer_data_i $1342 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 $1344 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $1345 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \write_en$1288 + connect \B \write_en$1303 + connect \Y $1345 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $1347 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \write_en$1318 + connect \B \write_en$1333 + connect \Y $1347 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 $1349 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $1345 + connect \B $1347 + connect \Y $1349 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A $1349 + connect \Y $1344 + end + process $group_442 + assign \xer_wen 3'000 + assign \xer_wen $1344 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_alu0_xer_ov_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1097 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1098 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1352 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165636,17 +166848,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok connect \B \fus_cu_busy_o - connect \Y $1097 + connect \Y $1352 end - process $group_384 + process $group_443 assign \wrflag_alu0_xer_ov_3 1'0 - assign \wrflag_alu0_xer_ov_3 $1097 + assign \wrflag_alu0_xer_ov_3 $1352 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1099 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1354 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165654,12 +166866,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [3] connect \B \fu_enable [0] - connect \Y $1099 + connect \Y $1354 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1356 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165667,12 +166879,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$90 [4] connect \B \fu_enable [5] - connect \Y $1101 + connect \Y $1356 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1358 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165680,12 +166892,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [2] connect \B \fu_enable [6] - connect \Y $1103 + connect \Y $1358 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1360 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165693,22 +166905,22 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [2] connect \B \fu_enable [7] - connect \Y $1105 + connect \Y $1360 end - process $group_385 + process $group_444 assign \wrpick_XER_xer_ov_i 4'0000 - assign \wrpick_XER_xer_ov_i [0] $1099 - assign \wrpick_XER_xer_ov_i [1] $1101 - assign \wrpick_XER_xer_ov_i [2] $1103 - assign \wrpick_XER_xer_ov_i [3] $1105 + assign \wrpick_XER_xer_ov_i [0] $1354 + assign \wrpick_XER_xer_ov_i [1] $1356 + assign \wrpick_XER_xer_ov_i [2] $1358 + assign \wrpick_XER_xer_ov_i [3] $1360 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1362 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165716,150 +166928,94 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [0] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1108 + connect \Y $1363 end - process $group_386 - assign \wr_pick$1107 1'0 - assign \wr_pick$1107 $1108 + process $group_445 + assign \wr_pick$1362 1'0 + assign \wr_pick$1362 $1363 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1110 + wire width 1 \wr_pick_dly$1365 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1110$next - process $group_387 - assign \wr_pick_dly$1110$next \wr_pick_dly$1110 - assign \wr_pick_dly$1110$next \wr_pick$1107 + wire width 1 \wr_pick_dly$1365$next + process $group_446 + assign \wr_pick_dly$1365$next \wr_pick_dly$1365 + assign \wr_pick_dly$1365$next \wr_pick$1362 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1110$next 1'0 + assign \wr_pick_dly$1365$next 1'0 end sync init - update \wr_pick_dly$1110 1'0 + update \wr_pick_dly$1365 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1110 \wr_pick_dly$1110$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1111 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1110 - connect \Y $1111 + update \wr_pick_dly$1365 \wr_pick_dly$1365$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1113 + wire width 1 $1366 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1114 + cell $not $1367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1107 - connect \B $1111 - connect \Y $1113 - end - process $group_388 - assign \wr_pick_rise$716 1'0 - assign \wr_pick_rise$716 $1113 - sync init + connect \A \wr_pick_dly$1365 + connect \Y $1366 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1116 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1368 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1107 - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1115 + connect \A \wr_pick$1362 + connect \B $1366 + connect \Y $1368 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1117 - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1118 + process $group_447 + assign \wr_pick_rise$877 1'0 + assign \wr_pick_rise$877 $1368 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 3 \write_en$1370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 3 $1371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1372 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1120 + connect \A \wr_pick$1362 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1121 + connect \Y $1372 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1123 - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1374 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S $1372 + connect \Y $1371 end - process $group_389 - assign \xer_wen$153 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1115 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \xer_wen$153 3'100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1118 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \xer_wen$153 3'100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1121 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \xer_wen$153 3'100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1124 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \xer_wen$153 3'100 - end + process $group_448 + assign \write_en$1370 3'000 + assign \write_en$1370 $1371 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_spr0_xer_ov_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165867,17 +167023,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$126 connect \B \fus_cu_busy_o$16 - connect \Y $1126 + connect \Y $1375 end - process $group_390 + process $group_449 assign \wrflag_spr0_xer_ov_4 1'0 - assign \wrflag_spr0_xer_ov_4 $1126 + assign \wrflag_spr0_xer_ov_4 $1375 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1377 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1378 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165885,64 +167043,94 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [1] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1128 + connect \Y $1378 end - process $group_391 - assign \wr_pick$1117 1'0 - assign \wr_pick$1117 $1128 + process $group_450 + assign \wr_pick$1377 1'0 + assign \wr_pick$1377 $1378 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1130 + wire width 1 \wr_pick_dly$1380 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1130$next - process $group_392 - assign \wr_pick_dly$1130$next \wr_pick_dly$1130 - assign \wr_pick_dly$1130$next \wr_pick$1117 + wire width 1 \wr_pick_dly$1380$next + process $group_451 + assign \wr_pick_dly$1380$next \wr_pick_dly$1380 + assign \wr_pick_dly$1380$next \wr_pick$1377 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1130$next 1'0 + assign \wr_pick_dly$1380$next 1'0 end sync init - update \wr_pick_dly$1130 1'0 + update \wr_pick_dly$1380 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1130 \wr_pick_dly$1130$next + update \wr_pick_dly$1380 \wr_pick_dly$1380$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1131 + wire width 1 $1381 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1132 + cell $not $1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1130 - connect \Y $1131 + connect \A \wr_pick_dly$1380 + connect \Y $1381 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1133 + wire width 1 $1383 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1134 + cell $and $1384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1117 - connect \B $1131 - connect \Y $1133 + connect \A \wr_pick$1377 + connect \B $1381 + connect \Y $1383 end - process $group_393 - assign \wr_pick_rise$816 1'0 - assign \wr_pick_rise$816 $1133 + process $group_452 + assign \wr_pick_rise$960 1'0 + assign \wr_pick_rise$960 $1383 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 3 \write_en$1385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 3 $1386 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1387 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1377 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $1387 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1389 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S $1387 + connect \Y $1386 + end + process $group_453 + assign \write_en$1385 3'000 + assign \write_en$1385 $1386 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_div0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165950,17 +167138,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$127 connect \B \fus_cu_busy_o$19 - connect \Y $1135 + connect \Y $1390 end - process $group_394 + process $group_454 assign \wrflag_div0_xer_ov_2 1'0 - assign \wrflag_div0_xer_ov_2 $1135 + assign \wrflag_div0_xer_ov_2 $1390 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165968,64 +167158,94 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [2] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1137 + connect \Y $1393 end - process $group_395 - assign \wr_pick$1120 1'0 - assign \wr_pick$1120 $1137 + process $group_455 + assign \wr_pick$1392 1'0 + assign \wr_pick$1392 $1393 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1139 + wire width 1 \wr_pick_dly$1395 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1139$next - process $group_396 - assign \wr_pick_dly$1139$next \wr_pick_dly$1139 - assign \wr_pick_dly$1139$next \wr_pick$1120 + wire width 1 \wr_pick_dly$1395$next + process $group_456 + assign \wr_pick_dly$1395$next \wr_pick_dly$1395 + assign \wr_pick_dly$1395$next \wr_pick$1392 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1139$next 1'0 + assign \wr_pick_dly$1395$next 1'0 end sync init - update \wr_pick_dly$1139 1'0 + update \wr_pick_dly$1395 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1139 \wr_pick_dly$1139$next + update \wr_pick_dly$1395 \wr_pick_dly$1395$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1140 + wire width 1 $1396 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1141 + cell $not $1397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1139 - connect \Y $1140 + connect \A \wr_pick_dly$1395 + connect \Y $1396 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1142 + wire width 1 $1398 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1143 + cell $and $1399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1120 - connect \B $1140 - connect \Y $1142 + connect \A \wr_pick$1392 + connect \B $1396 + connect \Y $1398 end - process $group_397 - assign \wr_pick_rise$831 1'0 - assign \wr_pick_rise$831 $1142 + process $group_457 + assign \wr_pick_rise$983 1'0 + assign \wr_pick_rise$983 $1398 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 3 \write_en$1400 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 3 $1401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1392 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $1402 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1404 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S $1402 + connect \Y $1401 + end + process $group_458 + assign \write_en$1400 3'000 + assign \write_en$1400 $1401 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_mul0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166033,17 +167253,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$128 connect \B \fus_cu_busy_o$22 - connect \Y $1144 + connect \Y $1405 end - process $group_398 + process $group_459 assign \wrflag_mul0_xer_ov_2 1'0 - assign \wrflag_mul0_xer_ov_2 $1144 + assign \wrflag_mul0_xer_ov_2 $1405 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166051,62 +167273,92 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [3] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1146 + connect \Y $1408 end - process $group_399 - assign \wr_pick$1123 1'0 - assign \wr_pick$1123 $1146 + process $group_460 + assign \wr_pick$1407 1'0 + assign \wr_pick$1407 $1408 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1148 + wire width 1 \wr_pick_dly$1410 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1148$next - process $group_400 - assign \wr_pick_dly$1148$next \wr_pick_dly$1148 - assign \wr_pick_dly$1148$next \wr_pick$1123 + wire width 1 \wr_pick_dly$1410$next + process $group_461 + assign \wr_pick_dly$1410$next \wr_pick_dly$1410 + assign \wr_pick_dly$1410$next \wr_pick$1407 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1148$next 1'0 + assign \wr_pick_dly$1410$next 1'0 end sync init - update \wr_pick_dly$1148 1'0 + update \wr_pick_dly$1410 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1148 \wr_pick_dly$1148$next + update \wr_pick_dly$1410 \wr_pick_dly$1410$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1149 + wire width 1 $1411 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1150 + cell $not $1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1148 - connect \Y $1149 + connect \A \wr_pick_dly$1410 + connect \Y $1411 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1151 + wire width 1 $1413 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1152 + cell $and $1414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1123 - connect \B $1149 - connect \Y $1151 + connect \A \wr_pick$1407 + connect \B $1411 + connect \Y $1413 end - process $group_401 - assign \wr_pick_rise$844 1'0 - assign \wr_pick_rise$844 $1151 + process $group_462 + assign \wr_pick_rise$1004 1'0 + assign \wr_pick_rise$1004 $1413 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 3 \write_en$1415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 3 $1416 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1417 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1407 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $1417 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1419 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S $1417 + connect \Y $1416 + end + process $group_463 + assign \write_en$1415 3'000 + assign \write_en$1415 $1416 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1153 + wire width 2 $1420 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1154 + cell $or $1421 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -166114,12 +167366,12 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest4_o connect \B \fus_dest5_o - connect \Y $1153 + connect \Y $1420 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1155 + wire width 2 $1422 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1156 + cell $or $1423 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -166127,32 +167379,76 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest3_o$129 connect \B \fus_dest3_o$130 - connect \Y $1155 + connect \Y $1422 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $1157 + wire width 2 $1424 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1158 + cell $or $1425 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $1153 - connect \B $1155 - connect \Y $1157 + connect \A $1420 + connect \B $1422 + connect \Y $1424 end - process $group_402 - assign \xer_data_i$154 2'00 - assign \xer_data_i$154 $1157 + process $group_464 + assign \xer_data_i$153 2'00 + assign \xer_data_i$153 $1424 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 3 $1426 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \write_en$1370 + connect \B \write_en$1385 + connect \Y $1426 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 3 $1428 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \write_en$1400 + connect \B \write_en$1415 + connect \Y $1428 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 $1430 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $1426 + connect \B $1428 + connect \Y $1430 + end + process $group_465 + assign \xer_wen$154 3'000 + assign \xer_wen$154 $1430 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_alu0_xer_so_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1432 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166160,17 +167456,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok connect \B \fus_cu_busy_o - connect \Y $1159 + connect \Y $1432 end - process $group_403 + process $group_466 assign \wrflag_alu0_xer_so_4 1'0 - assign \wrflag_alu0_xer_so_4 $1159 + assign \wrflag_alu0_xer_so_4 $1432 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1434 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166178,12 +167474,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [4] connect \B \fu_enable [0] - connect \Y $1161 + connect \Y $1434 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1436 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166191,12 +167487,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$90 [3] connect \B \fu_enable [5] - connect \Y $1163 + connect \Y $1436 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1438 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166204,12 +167500,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [3] connect \B \fu_enable [6] - connect \Y $1165 + connect \Y $1438 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1440 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166217,22 +167513,22 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [3] connect \B \fu_enable [7] - connect \Y $1167 + connect \Y $1440 end - process $group_404 + process $group_467 assign \wrpick_XER_xer_so_i 4'0000 - assign \wrpick_XER_xer_so_i [0] $1161 - assign \wrpick_XER_xer_so_i [1] $1163 - assign \wrpick_XER_xer_so_i [2] $1165 - assign \wrpick_XER_xer_so_i [3] $1167 + assign \wrpick_XER_xer_so_i [0] $1434 + assign \wrpick_XER_xer_so_i [1] $1436 + assign \wrpick_XER_xer_so_i [2] $1438 + assign \wrpick_XER_xer_so_i [3] $1440 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1442 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166240,150 +167536,94 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [0] connect \B \wrpick_XER_xer_so_en_o - connect \Y $1170 + connect \Y $1443 end - process $group_405 - assign \wr_pick$1169 1'0 - assign \wr_pick$1169 $1170 + process $group_468 + assign \wr_pick$1442 1'0 + assign \wr_pick$1442 $1443 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1172 + wire width 1 \wr_pick_dly$1445 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1172$next - process $group_406 - assign \wr_pick_dly$1172$next \wr_pick_dly$1172 - assign \wr_pick_dly$1172$next \wr_pick$1169 + wire width 1 \wr_pick_dly$1445$next + process $group_469 + assign \wr_pick_dly$1445$next \wr_pick_dly$1445 + assign \wr_pick_dly$1445$next \wr_pick$1442 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1172$next 1'0 + assign \wr_pick_dly$1445$next 1'0 end sync init - update \wr_pick_dly$1172 1'0 + update \wr_pick_dly$1445 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1172 \wr_pick_dly$1172$next + update \wr_pick_dly$1445 \wr_pick_dly$1445$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1173 + wire width 1 $1446 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1174 + cell $not $1447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1172 - connect \Y $1173 + connect \A \wr_pick_dly$1445 + connect \Y $1446 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1175 + wire width 1 $1448 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1176 + cell $and $1449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1169 - connect \B $1173 - connect \Y $1175 + connect \A \wr_pick$1442 + connect \B $1446 + connect \Y $1448 end - process $group_407 - assign \wr_pick_rise$717 1'0 - assign \wr_pick_rise$717 $1175 + process $group_470 + assign \wr_pick_rise$878 1'0 + assign \wr_pick_rise$878 $1448 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1169 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1177 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1179 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1180 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 1 \write_en$1450 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1451 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1452 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1182 + connect \A \wr_pick$1442 connect \B \wrpick_XER_xer_so_en_o - connect \Y $1183 + connect \Y $1452 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1185 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1454 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $1452 + connect \Y $1451 end - process $group_408 - assign \xer_wen$155 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1177 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \xer_wen$155 3'001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1180 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \xer_wen$155 3'001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1183 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \xer_wen$155 3'001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1186 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \xer_wen$155 3'001 - end + process $group_471 + assign \write_en$1450 1'0 + assign \write_en$1450 $1451 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_spr0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1455 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166391,17 +167631,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$131 connect \B \fus_cu_busy_o$16 - connect \Y $1188 + connect \Y $1455 end - process $group_409 + process $group_472 assign \wrflag_spr0_xer_so_3 1'0 - assign \wrflag_spr0_xer_so_3 $1188 + assign \wrflag_spr0_xer_so_3 $1455 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1458 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166409,64 +167651,94 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [1] connect \B \wrpick_XER_xer_so_en_o - connect \Y $1190 + connect \Y $1458 end - process $group_410 - assign \wr_pick$1179 1'0 - assign \wr_pick$1179 $1190 + process $group_473 + assign \wr_pick$1457 1'0 + assign \wr_pick$1457 $1458 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1192 + wire width 1 \wr_pick_dly$1460 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1192$next - process $group_411 - assign \wr_pick_dly$1192$next \wr_pick_dly$1192 - assign \wr_pick_dly$1192$next \wr_pick$1179 + wire width 1 \wr_pick_dly$1460$next + process $group_474 + assign \wr_pick_dly$1460$next \wr_pick_dly$1460 + assign \wr_pick_dly$1460$next \wr_pick$1457 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1192$next 1'0 + assign \wr_pick_dly$1460$next 1'0 end sync init - update \wr_pick_dly$1192 1'0 + update \wr_pick_dly$1460 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1192 \wr_pick_dly$1192$next + update \wr_pick_dly$1460 \wr_pick_dly$1460$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1193 + wire width 1 $1461 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1194 + cell $not $1462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1192 - connect \Y $1193 + connect \A \wr_pick_dly$1460 + connect \Y $1461 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1195 + wire width 1 $1463 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1196 + cell $and $1464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1179 - connect \B $1193 - connect \Y $1195 + connect \A \wr_pick$1457 + connect \B $1461 + connect \Y $1463 end - process $group_412 - assign \wr_pick_rise$817 1'0 - assign \wr_pick_rise$817 $1195 + process $group_475 + assign \wr_pick_rise$961 1'0 + assign \wr_pick_rise$961 $1463 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 1 \write_en$1465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1457 + connect \B \wrpick_XER_xer_so_en_o + connect \Y $1467 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1469 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $1467 + connect \Y $1466 + end + process $group_476 + assign \write_en$1465 1'0 + assign \write_en$1465 $1466 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_div0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1470 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166474,17 +167746,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$132 connect \B \fus_cu_busy_o$19 - connect \Y $1197 + connect \Y $1470 end - process $group_413 + process $group_477 assign \wrflag_div0_xer_so_3 1'0 - assign \wrflag_div0_xer_so_3 $1197 + assign \wrflag_div0_xer_so_3 $1470 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1199 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1473 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166492,64 +167766,94 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [2] connect \B \wrpick_XER_xer_so_en_o - connect \Y $1199 + connect \Y $1473 end - process $group_414 - assign \wr_pick$1182 1'0 - assign \wr_pick$1182 $1199 + process $group_478 + assign \wr_pick$1472 1'0 + assign \wr_pick$1472 $1473 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1201 + wire width 1 \wr_pick_dly$1475 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1201$next - process $group_415 - assign \wr_pick_dly$1201$next \wr_pick_dly$1201 - assign \wr_pick_dly$1201$next \wr_pick$1182 + wire width 1 \wr_pick_dly$1475$next + process $group_479 + assign \wr_pick_dly$1475$next \wr_pick_dly$1475 + assign \wr_pick_dly$1475$next \wr_pick$1472 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1201$next 1'0 + assign \wr_pick_dly$1475$next 1'0 end sync init - update \wr_pick_dly$1201 1'0 + update \wr_pick_dly$1475 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1201 \wr_pick_dly$1201$next + update \wr_pick_dly$1475 \wr_pick_dly$1475$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1202 + wire width 1 $1476 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1203 + cell $not $1477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1201 - connect \Y $1202 + connect \A \wr_pick_dly$1475 + connect \Y $1476 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1204 + wire width 1 $1478 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1205 + cell $and $1479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1182 - connect \B $1202 - connect \Y $1204 + connect \A \wr_pick$1472 + connect \B $1476 + connect \Y $1478 end - process $group_416 - assign \wr_pick_rise$832 1'0 - assign \wr_pick_rise$832 $1204 + process $group_480 + assign \wr_pick_rise$984 1'0 + assign \wr_pick_rise$984 $1478 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 1 \write_en$1480 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1481 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1482 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1472 + connect \B \wrpick_XER_xer_so_en_o + connect \Y $1482 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1484 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $1482 + connect \Y $1481 + end + process $group_481 + assign \write_en$1480 1'0 + assign \write_en$1480 $1481 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_mul0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1485 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166557,17 +167861,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$133 connect \B \fus_cu_busy_o$22 - connect \Y $1206 + connect \Y $1485 end - process $group_417 + process $group_482 assign \wrflag_mul0_xer_so_3 1'0 - assign \wrflag_mul0_xer_so_3 $1206 + assign \wrflag_mul0_xer_so_3 $1485 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1487 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1488 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166575,64 +167881,94 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [3] connect \B \wrpick_XER_xer_so_en_o - connect \Y $1208 + connect \Y $1488 end - process $group_418 - assign \wr_pick$1185 1'0 - assign \wr_pick$1185 $1208 + process $group_483 + assign \wr_pick$1487 1'0 + assign \wr_pick$1487 $1488 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1210 + wire width 1 \wr_pick_dly$1490 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1210$next - process $group_419 - assign \wr_pick_dly$1210$next \wr_pick_dly$1210 - assign \wr_pick_dly$1210$next \wr_pick$1185 + wire width 1 \wr_pick_dly$1490$next + process $group_484 + assign \wr_pick_dly$1490$next \wr_pick_dly$1490 + assign \wr_pick_dly$1490$next \wr_pick$1487 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1210$next 1'0 + assign \wr_pick_dly$1490$next 1'0 end sync init - update \wr_pick_dly$1210 1'0 + update \wr_pick_dly$1490 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1210 \wr_pick_dly$1210$next + update \wr_pick_dly$1490 \wr_pick_dly$1490$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1211 + wire width 1 $1491 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1212 + cell $not $1492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1210 - connect \Y $1211 + connect \A \wr_pick_dly$1490 + connect \Y $1491 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1213 + wire width 1 $1493 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1214 + cell $and $1494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1185 - connect \B $1211 - connect \Y $1213 + connect \A \wr_pick$1487 + connect \B $1491 + connect \Y $1493 end - process $group_420 - assign \wr_pick_rise$845 1'0 - assign \wr_pick_rise$845 $1213 + process $group_485 + assign \wr_pick_rise$1005 1'0 + assign \wr_pick_rise$1005 $1493 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 1 \write_en$1495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1497 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1487 + connect \B \wrpick_XER_xer_so_en_o + connect \Y $1497 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1499 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $1497 + connect \Y $1496 + end + process $group_486 + assign \write_en$1495 1'0 + assign \write_en$1495 $1496 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $1215 + wire width 2 $1500 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1216 + wire width 1 $1501 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1217 + cell $or $1502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166640,12 +167976,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_dest5_o$134 connect \B \fus_dest4_o$135 - connect \Y $1216 + connect \Y $1501 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1218 + wire width 1 $1503 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1219 + cell $or $1504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166653,40 +167989,94 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_dest4_o$136 connect \B \fus_dest4_o$137 - connect \Y $1218 + connect \Y $1503 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1220 + wire width 1 $1505 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1221 + cell $or $1506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $1216 - connect \B $1218 - connect \Y $1220 + connect \A $1501 + connect \B $1503 + connect \Y $1505 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $1222 + cell $pos $1507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 - connect \A $1220 - connect \Y $1215 + connect \A $1505 + connect \Y $1500 end - process $group_421 - assign \xer_data_i$156 2'00 - assign \xer_data_i$156 $1215 + process $group_487 + assign \xer_data_i$155 2'00 + assign \xer_data_i$155 $1500 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 $1508 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $1509 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \write_en$1450 + connect \B \write_en$1465 + connect \Y $1509 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $1511 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \write_en$1480 + connect \B \write_en$1495 + connect \Y $1511 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 1 $1513 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1509 + connect \B $1511 + connect \Y $1513 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $1515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A $1513 + connect \Y $1508 + end + process $group_488 + assign \xer_wen$156 3'000 + assign \xer_wen$156 $1508 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_branch0_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1223 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1516 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166694,17 +168084,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok connect \B \fus_cu_busy_o$7 - connect \Y $1223 + connect \Y $1516 end - process $group_422 + process $group_489 assign \wrflag_branch0_fast1_0 1'0 - assign \wrflag_branch0_fast1_0 $1223 + assign \wrflag_branch0_fast1_0 $1516 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1225 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166712,12 +168102,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$138 [0] connect \B \fu_enable [2] - connect \Y $1225 + connect \Y $1518 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1227 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166725,12 +168115,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$84 [1] connect \B \fu_enable [3] - connect \Y $1227 + connect \Y $1520 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1229 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166738,12 +168128,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$90 [2] connect \B \fu_enable [5] - connect \Y $1229 + connect \Y $1522 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1231 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1232 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166751,12 +168141,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$138 [1] connect \B \fu_enable [2] - connect \Y $1231 + connect \Y $1524 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1233 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1234 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166764,23 +168154,23 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$84 [2] connect \B \fu_enable [3] - connect \Y $1233 + connect \Y $1526 end - process $group_423 + process $group_490 assign \wrpick_FAST_fast1_i 5'00000 - assign \wrpick_FAST_fast1_i [0] $1225 - assign \wrpick_FAST_fast1_i [1] $1227 - assign \wrpick_FAST_fast1_i [2] $1229 - assign \wrpick_FAST_fast1_i [3] $1231 - assign \wrpick_FAST_fast1_i [4] $1233 + assign \wrpick_FAST_fast1_i [0] $1518 + assign \wrpick_FAST_fast1_i [1] $1520 + assign \wrpick_FAST_fast1_i [2] $1522 + assign \wrpick_FAST_fast1_i [3] $1524 + assign \wrpick_FAST_fast1_i [4] $1526 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1235 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1237 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166788,152 +168178,77 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [0] connect \B \wrpick_FAST_fast1_en_o - connect \Y $1236 + connect \Y $1529 end - process $group_424 - assign \wr_pick$1235 1'0 - assign \wr_pick$1235 $1236 + process $group_491 + assign \wr_pick$1528 1'0 + assign \wr_pick$1528 $1529 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1238 + wire width 1 \wr_pick_dly$1531 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1238$next - process $group_425 - assign \wr_pick_dly$1238$next \wr_pick_dly$1238 - assign \wr_pick_dly$1238$next \wr_pick$1235 + wire width 1 \wr_pick_dly$1531$next + process $group_492 + assign \wr_pick_dly$1531$next \wr_pick_dly$1531 + assign \wr_pick_dly$1531$next \wr_pick$1528 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1238$next 1'0 + assign \wr_pick_dly$1531$next 1'0 end sync init - update \wr_pick_dly$1238 1'0 + update \wr_pick_dly$1531 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1238 \wr_pick_dly$1238$next + update \wr_pick_dly$1531 \wr_pick_dly$1531$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1239 + wire width 1 \wr_pick_rise$1532 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1240 + wire width 1 $1533 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1241 + cell $not $1534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1238 - connect \Y $1240 + connect \A \wr_pick_dly$1531 + connect \Y $1533 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1242 + wire width 1 $1535 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1243 + cell $and $1536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1235 - connect \B $1240 - connect \Y $1242 + connect \A \wr_pick$1528 + connect \B $1533 + connect \Y $1535 end - process $group_426 - assign \wr_pick_rise$1239 1'0 - assign \wr_pick_rise$1239 $1242 + process $group_493 + assign \wr_pick_rise$1532 1'0 + assign \wr_pick_rise$1532 $1535 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1244 + wire width 1 \wr_pick_rise$1537 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1245 - process $group_427 + wire width 1 \wr_pick_rise$1538 + process $group_494 assign \fus_cu_wr__go_i$139 3'000 - assign \fus_cu_wr__go_i$139 [0] \wr_pick_rise$1239 - assign \fus_cu_wr__go_i$139 [1] \wr_pick_rise$1244 - assign \fus_cu_wr__go_i$139 [2] \wr_pick_rise$1245 + assign \fus_cu_wr__go_i$139 [0] \wr_pick_rise$1532 + assign \fus_cu_wr__go_i$139 [1] \wr_pick_rise$1537 + assign \fus_cu_wr__go_i$139 [2] \wr_pick_rise$1538 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1246 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1235 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1246 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - wire width 8 $1248 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - wire width 8 $1249 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - cell $sshl $1250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fasto1 - connect \Y $1249 - end - connect $1248 $1249 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1251 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1252 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1251 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1252 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - wire width 8 $1254 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - wire width 8 $1255 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - cell $sshl $1256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fasto1 - connect \Y $1255 - end - connect $1254 $1255 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1257 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1258 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1257 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1258 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - wire width 8 $1260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 8 \write_en$1539 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - wire width 8 $1261 + wire width 8 $1540 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - cell $sshl $1262 + cell $sshl $1541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -166941,111 +168256,42 @@ module \core parameter \Y_WIDTH 8 connect \A 1'1 connect \B \pdecode2_fasto1 - connect \Y $1261 - end - connect $1260 $1261 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1263 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1264 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1263 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1264 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180" - wire width 8 $1266 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180" - wire width 8 $1267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180" - cell $sshl $1268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fasto2 - connect \Y $1267 + connect \Y $1540 end - connect $1266 $1267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1269 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 8 $1542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1269 + connect \A \wr_pick$1528 connect \B \wrpick_FAST_fast1_en_o - connect \Y $1270 + connect \Y $1543 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180" - wire width 8 $1272 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180" - wire width 8 $1273 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180" - cell $sshl $1274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fasto2 - connect \Y $1273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1545 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B $1540 + connect \S $1543 + connect \Y $1542 end - connect $1272 $1273 - process $group_428 - assign \fast_wen 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1246 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \fast_wen $1248 [4:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1252 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \fast_wen $1254 [4:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1258 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \fast_wen $1260 [4:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1264 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \fast_wen $1266 [4:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1270 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \fast_wen $1272 [4:0] - end + process $group_495 + assign \write_en$1539 8'00000000 + assign \write_en$1539 $1542 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_trap0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1275 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167053,17 +168299,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok$140 connect \B \fus_cu_busy_o$10 - connect \Y $1275 + connect \Y $1546 end - process $group_429 + process $group_496 assign \wrflag_trap0_fast1_1 1'0 - assign \wrflag_trap0_fast1_1 $1275 + assign \wrflag_trap0_fast1_1 $1546 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1277 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167071,64 +168319,107 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [1] connect \B \wrpick_FAST_fast1_en_o - connect \Y $1277 + connect \Y $1549 end - process $group_430 - assign \wr_pick$1251 1'0 - assign \wr_pick$1251 $1277 + process $group_497 + assign \wr_pick$1548 1'0 + assign \wr_pick$1548 $1549 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1279 + wire width 1 \wr_pick_dly$1551 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1279$next - process $group_431 - assign \wr_pick_dly$1279$next \wr_pick_dly$1279 - assign \wr_pick_dly$1279$next \wr_pick$1251 + wire width 1 \wr_pick_dly$1551$next + process $group_498 + assign \wr_pick_dly$1551$next \wr_pick_dly$1551 + assign \wr_pick_dly$1551$next \wr_pick$1548 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1279$next 1'0 + assign \wr_pick_dly$1551$next 1'0 end sync init - update \wr_pick_dly$1279 1'0 + update \wr_pick_dly$1551 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1279 \wr_pick_dly$1279$next + update \wr_pick_dly$1551 \wr_pick_dly$1551$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1280 + wire width 1 $1552 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1281 + cell $not $1553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1279 - connect \Y $1280 + connect \A \wr_pick_dly$1551 + connect \Y $1552 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1282 + wire width 1 $1554 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1283 + cell $and $1555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1251 - connect \B $1280 - connect \Y $1282 + connect \A \wr_pick$1548 + connect \B $1552 + connect \Y $1554 end - process $group_432 - assign \wr_pick_rise$789 1'0 - assign \wr_pick_rise$789 $1282 + process $group_499 + assign \wr_pick_rise$917 1'0 + assign \wr_pick_rise$917 $1554 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 8 \write_en$1556 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" + wire width 8 $1557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" + cell $sshl $1558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 8 + connect \A 1'1 + connect \B \pdecode2_fasto1 + connect \Y $1557 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 8 $1559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1548 + connect \B \wrpick_FAST_fast1_en_o + connect \Y $1560 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1562 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B $1557 + connect \S $1560 + connect \Y $1559 + end + process $group_500 + assign \write_en$1556 8'00000000 + assign \write_en$1556 $1559 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_spr0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1284 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1563 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167136,17 +168427,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok$141 connect \B \fus_cu_busy_o$16 - connect \Y $1284 + connect \Y $1563 end - process $group_433 + process $group_501 assign \wrflag_spr0_fast1_2 1'0 - assign \wrflag_spr0_fast1_2 $1284 + assign \wrflag_spr0_fast1_2 $1563 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1286 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1566 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167154,64 +168447,107 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [2] connect \B \wrpick_FAST_fast1_en_o - connect \Y $1286 + connect \Y $1566 end - process $group_434 - assign \wr_pick$1257 1'0 - assign \wr_pick$1257 $1286 + process $group_502 + assign \wr_pick$1565 1'0 + assign \wr_pick$1565 $1566 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1288 + wire width 1 \wr_pick_dly$1568 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1288$next - process $group_435 - assign \wr_pick_dly$1288$next \wr_pick_dly$1288 - assign \wr_pick_dly$1288$next \wr_pick$1257 + wire width 1 \wr_pick_dly$1568$next + process $group_503 + assign \wr_pick_dly$1568$next \wr_pick_dly$1568 + assign \wr_pick_dly$1568$next \wr_pick$1565 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1288$next 1'0 + assign \wr_pick_dly$1568$next 1'0 end sync init - update \wr_pick_dly$1288 1'0 + update \wr_pick_dly$1568 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1288 \wr_pick_dly$1288$next + update \wr_pick_dly$1568 \wr_pick_dly$1568$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1289 + wire width 1 $1569 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1290 + cell $not $1570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1288 - connect \Y $1289 + connect \A \wr_pick_dly$1568 + connect \Y $1569 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1291 + wire width 1 $1571 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1292 + cell $and $1572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1565 + connect \B $1569 + connect \Y $1571 + end + process $group_504 + assign \wr_pick_rise$962 1'0 + assign \wr_pick_rise$962 $1571 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 8 \write_en$1573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" + wire width 8 $1574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" + cell $sshl $1575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 8 + connect \A 1'1 + connect \B \pdecode2_fasto1 + connect \Y $1574 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 8 $1576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1257 - connect \B $1289 - connect \Y $1291 + connect \A \wr_pick$1565 + connect \B \wrpick_FAST_fast1_en_o + connect \Y $1577 end - process $group_436 - assign \wr_pick_rise$818 1'0 - assign \wr_pick_rise$818 $1291 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1579 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B $1574 + connect \S $1577 + connect \Y $1576 + end + process $group_505 + assign \write_en$1573 8'00000000 + assign \write_en$1573 $1576 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_branch0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1293 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1294 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1580 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167219,17 +168555,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast2_ok connect \B \fus_cu_busy_o$7 - connect \Y $1293 + connect \Y $1580 end - process $group_437 + process $group_506 assign \wrflag_branch0_fast1_1 1'0 - assign \wrflag_branch0_fast1_1 $1293 + assign \wrflag_branch0_fast1_1 $1580 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1295 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1582 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167237,64 +168575,107 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [3] connect \B \wrpick_FAST_fast1_en_o - connect \Y $1295 + connect \Y $1583 end - process $group_438 - assign \wr_pick$1263 1'0 - assign \wr_pick$1263 $1295 + process $group_507 + assign \wr_pick$1582 1'0 + assign \wr_pick$1582 $1583 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1297 + wire width 1 \wr_pick_dly$1585 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1297$next - process $group_439 - assign \wr_pick_dly$1297$next \wr_pick_dly$1297 - assign \wr_pick_dly$1297$next \wr_pick$1263 + wire width 1 \wr_pick_dly$1585$next + process $group_508 + assign \wr_pick_dly$1585$next \wr_pick_dly$1585 + assign \wr_pick_dly$1585$next \wr_pick$1582 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1297$next 1'0 + assign \wr_pick_dly$1585$next 1'0 end sync init - update \wr_pick_dly$1297 1'0 + update \wr_pick_dly$1585 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1297 \wr_pick_dly$1297$next + update \wr_pick_dly$1585 \wr_pick_dly$1585$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1298 + wire width 1 $1586 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1299 + cell $not $1587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1297 - connect \Y $1298 + connect \A \wr_pick_dly$1585 + connect \Y $1586 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1300 + wire width 1 $1588 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1301 + cell $and $1589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1263 - connect \B $1298 - connect \Y $1300 + connect \A \wr_pick$1582 + connect \B $1586 + connect \Y $1588 end - process $group_440 - assign \wr_pick_rise$1244 1'0 - assign \wr_pick_rise$1244 $1300 + process $group_509 + assign \wr_pick_rise$1537 1'0 + assign \wr_pick_rise$1537 $1588 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 8 \write_en$1590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180" + wire width 8 $1591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180" + cell $sshl $1592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 8 + connect \A 1'1 + connect \B \pdecode2_fasto2 + connect \Y $1591 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 8 $1593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1582 + connect \B \wrpick_FAST_fast1_en_o + connect \Y $1594 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1596 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B $1591 + connect \S $1594 + connect \Y $1593 + end + process $group_510 + assign \write_en$1590 8'00000000 + assign \write_en$1590 $1593 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_trap0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1302 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1303 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1597 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167302,17 +168683,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast2_ok$142 connect \B \fus_cu_busy_o$10 - connect \Y $1302 + connect \Y $1597 end - process $group_441 + process $group_511 assign \wrflag_trap0_fast1_2 1'0 - assign \wrflag_trap0_fast1_2 $1302 + assign \wrflag_trap0_fast1_2 $1597 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1304 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1600 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167320,62 +168703,105 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [4] connect \B \wrpick_FAST_fast1_en_o - connect \Y $1304 + connect \Y $1600 end - process $group_442 - assign \wr_pick$1269 1'0 - assign \wr_pick$1269 $1304 + process $group_512 + assign \wr_pick$1599 1'0 + assign \wr_pick$1599 $1600 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1306 + wire width 1 \wr_pick_dly$1602 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1306$next - process $group_443 - assign \wr_pick_dly$1306$next \wr_pick_dly$1306 - assign \wr_pick_dly$1306$next \wr_pick$1269 + wire width 1 \wr_pick_dly$1602$next + process $group_513 + assign \wr_pick_dly$1602$next \wr_pick_dly$1602 + assign \wr_pick_dly$1602$next \wr_pick$1599 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1306$next 1'0 + assign \wr_pick_dly$1602$next 1'0 end sync init - update \wr_pick_dly$1306 1'0 + update \wr_pick_dly$1602 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1306 \wr_pick_dly$1306$next + update \wr_pick_dly$1602 \wr_pick_dly$1602$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1307 + wire width 1 $1603 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1308 + cell $not $1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1306 - connect \Y $1307 + connect \A \wr_pick_dly$1602 + connect \Y $1603 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1309 + wire width 1 $1605 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1310 + cell $and $1606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1269 - connect \B $1307 - connect \Y $1309 + connect \A \wr_pick$1599 + connect \B $1603 + connect \Y $1605 end - process $group_444 - assign \wr_pick_rise$790 1'0 - assign \wr_pick_rise$790 $1309 + process $group_514 + assign \wr_pick_rise$918 1'0 + assign \wr_pick_rise$918 $1605 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 8 \write_en$1607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180" + wire width 8 $1608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180" + cell $sshl $1609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 8 + connect \A 1'1 + connect \B \pdecode2_fasto2 + connect \Y $1608 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 8 $1610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1599 + connect \B \wrpick_FAST_fast1_en_o + connect \Y $1611 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1613 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B $1608 + connect \S $1611 + connect \Y $1610 + end + process $group_515 + assign \write_en$1607 8'00000000 + assign \write_en$1607 $1610 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1311 + wire width 64 $1614 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1312 + cell $or $1615 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -167383,12 +168809,12 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$143 connect \B \fus_dest2_o$144 - connect \Y $1311 + connect \Y $1614 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1313 + wire width 64 $1616 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1314 + cell $or $1617 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -167396,45 +168822,105 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest2_o$146 connect \B \fus_dest3_o$147 - connect \Y $1313 + connect \Y $1616 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $1315 + wire width 64 $1618 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1316 + cell $or $1619 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest3_o$145 - connect \B $1313 - connect \Y $1315 + connect \B $1616 + connect \Y $1618 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $1317 + wire width 64 $1620 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1318 + cell $or $1621 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $1311 - connect \B $1315 - connect \Y $1317 + connect \A $1614 + connect \B $1618 + connect \Y $1620 end - process $group_445 + process $group_516 assign \fast_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast_data_i $1317 + assign \fast_data_i $1620 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 8 $1622 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 8 $1623 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \write_en$1539 + connect \B \write_en$1556 + connect \Y $1623 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 8 $1625 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \write_en$1590 + connect \B \write_en$1607 + connect \Y $1625 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 8 $1627 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \write_en$1573 + connect \B $1625 + connect \Y $1627 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 8 $1629 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $1623 + connect \B $1627 + connect \Y $1629 + end + connect $1622 $1629 + process $group_517 + assign \fast_wen 5'00000 + assign \fast_wen $1622 [4:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_branch0_nia_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1319 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167442,17 +168928,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_nia_ok connect \B \fus_cu_busy_o$7 - connect \Y $1319 + connect \Y $1631 end - process $group_446 + process $group_518 assign \wrflag_branch0_nia_2 1'0 - assign \wrflag_branch0_nia_2 $1319 + assign \wrflag_branch0_nia_2 $1631 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1321 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1322 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167460,12 +168946,12 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$138 [2] connect \B \fu_enable [2] - connect \Y $1321 + connect \Y $1633 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1323 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167473,20 +168959,20 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$84 [3] connect \B \fu_enable [3] - connect \Y $1323 + connect \Y $1635 end - process $group_447 + process $group_519 assign \wrpick_STATE_nia_i 2'00 - assign \wrpick_STATE_nia_i [0] $1321 - assign \wrpick_STATE_nia_i [1] $1323 + assign \wrpick_STATE_nia_i [0] $1633 + assign \wrpick_STATE_nia_i [1] $1635 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1325 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1326 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167494,108 +168980,94 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [0] connect \B \wrpick_STATE_nia_en_o - connect \Y $1326 + connect \Y $1638 end - process $group_448 - assign \wr_pick$1325 1'0 - assign \wr_pick$1325 $1326 + process $group_520 + assign \wr_pick$1637 1'0 + assign \wr_pick$1637 $1638 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1328 + wire width 1 \wr_pick_dly$1640 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1328$next - process $group_449 - assign \wr_pick_dly$1328$next \wr_pick_dly$1328 - assign \wr_pick_dly$1328$next \wr_pick$1325 + wire width 1 \wr_pick_dly$1640$next + process $group_521 + assign \wr_pick_dly$1640$next \wr_pick_dly$1640 + assign \wr_pick_dly$1640$next \wr_pick$1637 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1328$next 1'0 + assign \wr_pick_dly$1640$next 1'0 end sync init - update \wr_pick_dly$1328 1'0 + update \wr_pick_dly$1640 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1328 \wr_pick_dly$1328$next + update \wr_pick_dly$1640 \wr_pick_dly$1640$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1329 + wire width 1 $1641 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1330 + cell $not $1642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1328 - connect \Y $1329 + connect \A \wr_pick_dly$1640 + connect \Y $1641 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1331 + wire width 1 $1643 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1332 + cell $and $1644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1325 - connect \B $1329 - connect \Y $1331 + connect \A \wr_pick$1637 + connect \B $1641 + connect \Y $1643 end - process $group_450 - assign \wr_pick_rise$1245 1'0 - assign \wr_pick_rise$1245 $1331 + process $group_522 + assign \wr_pick_rise$1538 1'0 + assign \wr_pick_rise$1538 $1643 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1333 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 1 \write_en$1645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1647 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1325 + connect \A \wr_pick$1637 connect \B \wrpick_STATE_nia_en_o - connect \Y $1333 + connect \Y $1647 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1335 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1336 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1335 - connect \B \wrpick_STATE_nia_en_o - connect \Y $1336 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1649 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $1647 + connect \Y $1646 end - process $group_451 - assign \state_nia_wen 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1333 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \state_nia_wen 2'01 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1336 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \state_nia_wen 2'01 - end + process $group_523 + assign \write_en$1645 1'0 + assign \write_en$1645 $1646 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_trap0_nia_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1338 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1339 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167603,17 +169075,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_nia_ok$148 connect \B \fus_cu_busy_o$10 - connect \Y $1338 + connect \Y $1650 end - process $group_452 + process $group_524 assign \wrflag_trap0_nia_3 1'0 - assign \wrflag_trap0_nia_3 $1338 + assign \wrflag_trap0_nia_3 $1650 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1340 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1341 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167621,62 +169095,92 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [1] connect \B \wrpick_STATE_nia_en_o - connect \Y $1340 + connect \Y $1653 end - process $group_453 - assign \wr_pick$1335 1'0 - assign \wr_pick$1335 $1340 + process $group_525 + assign \wr_pick$1652 1'0 + assign \wr_pick$1652 $1653 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1342 + wire width 1 \wr_pick_dly$1655 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1342$next - process $group_454 - assign \wr_pick_dly$1342$next \wr_pick_dly$1342 - assign \wr_pick_dly$1342$next \wr_pick$1335 + wire width 1 \wr_pick_dly$1655$next + process $group_526 + assign \wr_pick_dly$1655$next \wr_pick_dly$1655 + assign \wr_pick_dly$1655$next \wr_pick$1652 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1342$next 1'0 + assign \wr_pick_dly$1655$next 1'0 end sync init - update \wr_pick_dly$1342 1'0 + update \wr_pick_dly$1655 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1342 \wr_pick_dly$1342$next + update \wr_pick_dly$1655 \wr_pick_dly$1655$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1343 + wire width 1 $1656 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1344 + cell $not $1657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1342 - connect \Y $1343 + connect \A \wr_pick_dly$1655 + connect \Y $1656 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1345 + wire width 1 $1658 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1346 + cell $and $1659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1335 - connect \B $1343 - connect \Y $1345 + connect \A \wr_pick$1652 + connect \B $1656 + connect \Y $1658 end - process $group_455 - assign \wr_pick_rise$791 1'0 - assign \wr_pick_rise$791 $1345 + process $group_527 + assign \wr_pick_rise$919 1'0 + assign \wr_pick_rise$919 $1658 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 1 \write_en$1660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1652 + connect \B \wrpick_STATE_nia_en_o + connect \Y $1662 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1664 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $1662 + connect \Y $1661 + end + process $group_528 + assign \write_en$1660 1'0 + assign \write_en$1660 $1661 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1347 + wire width 64 $1665 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1348 + cell $or $1666 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -167684,19 +169188,47 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest3_o$149 connect \B \fus_dest4_o$150 - connect \Y $1347 + connect \Y $1665 end - process $group_456 + process $group_529 assign \state_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \state_data_i $1347 + assign \state_data_i $1665 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $1667 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $1668 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \write_en$1645 + connect \B \write_en$1660 + connect \Y $1668 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $pos $1670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A $1668 + connect \Y $1667 + end + process $group_530 + assign \state_nia_wen 2'00 + assign \state_nia_wen $1667 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_trap0_msr_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1349 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1350 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167704,17 +169236,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_msr_ok connect \B \fus_cu_busy_o$10 - connect \Y $1349 + connect \Y $1671 end - process $group_457 + process $group_531 assign \wrflag_trap0_msr_4 1'0 - assign \wrflag_trap0_msr_4 $1349 + assign \wrflag_trap0_msr_4 $1671 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1351 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1352 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167722,19 +169254,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$84 [4] connect \B \fu_enable [3] - connect \Y $1351 + connect \Y $1673 end - process $group_458 + process $group_532 assign \wrpick_STATE_msr_i 1'0 - assign \wrpick_STATE_msr_i $1351 + assign \wrpick_STATE_msr_i $1673 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" - wire width 1 \wr_pick$1353 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1354 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1355 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1676 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167742,92 +169274,104 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_msr_o connect \B \wrpick_STATE_msr_en_o - connect \Y $1354 + connect \Y $1676 end - process $group_459 - assign \wr_pick$1353 1'0 - assign \wr_pick$1353 $1354 + process $group_533 + assign \wr_pick$1675 1'0 + assign \wr_pick$1675 $1676 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1356 + wire width 1 \wr_pick_dly$1678 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1356$next - process $group_460 - assign \wr_pick_dly$1356$next \wr_pick_dly$1356 - assign \wr_pick_dly$1356$next \wr_pick$1353 + wire width 1 \wr_pick_dly$1678$next + process $group_534 + assign \wr_pick_dly$1678$next \wr_pick_dly$1678 + assign \wr_pick_dly$1678$next \wr_pick$1675 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1356$next 1'0 + assign \wr_pick_dly$1678$next 1'0 end sync init - update \wr_pick_dly$1356 1'0 + update \wr_pick_dly$1678 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1356 \wr_pick_dly$1356$next + update \wr_pick_dly$1678 \wr_pick_dly$1678$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1357 + wire width 1 $1679 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1358 + cell $not $1680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1356 - connect \Y $1357 + connect \A \wr_pick_dly$1678 + connect \Y $1679 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1359 + wire width 1 $1681 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1360 + cell $and $1682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1353 - connect \B $1357 - connect \Y $1359 + connect \A \wr_pick$1675 + connect \B $1679 + connect \Y $1681 end - process $group_461 - assign \wr_pick_rise$792 1'0 - assign \wr_pick_rise$792 $1359 + process $group_535 + assign \wr_pick_rise$920 1'0 + assign \wr_pick_rise$920 $1681 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - wire width 1 $1361 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - cell $and $1362 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341" + wire width 2 \write_en$1683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 2 $1684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1353 + connect \A \wr_pick$1675 connect \B \wrpick_STATE_msr_en_o - connect \Y $1361 + connect \Y $1685 end - process $group_462 - assign \state_wen 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - switch { $1361 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" - case 1'1 - assign \state_wen 2'10 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1687 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S $1685 + connect \Y $1684 + end + process $group_536 + assign \write_en$1683 2'00 + assign \write_en$1683 $1684 sync init end - process $group_463 + process $group_537 assign \state_data_i$157 64'0000000000000000000000000000000000000000000000000000000000000000 assign \state_data_i$157 \fus_dest5_o$151 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319" + process $group_538 + assign \state_wen 2'00 + assign \state_wen \write_en$1683 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire width 1 \wrflag_spr0_spr1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - wire width 1 $1363 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $and $1364 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + wire width 1 $1688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" + cell $and $1689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167835,17 +169379,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_spr1_ok connect \B \fus_cu_busy_o$16 - connect \Y $1363 + connect \Y $1688 end - process $group_464 + process $group_539 assign \wrflag_spr0_spr1_1 1'0 - assign \wrflag_spr0_spr1_1 $1363 + assign \wrflag_spr0_spr1_1 $1688 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - wire width 1 $1365 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324" - cell $and $1366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + wire width 1 $1690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331" + cell $and $1691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167853,17 +169397,19 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$90 [1] connect \B \fu_enable [5] - connect \Y $1365 + connect \Y $1690 end - process $group_465 + process $group_540 assign \wrpick_SPR_spr1_i 1'0 - assign \wrpick_SPR_spr1_i $1365 + assign \wrpick_SPR_spr1_i $1690 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - wire width 1 $1367 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328" - cell $and $1368 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334" + wire width 1 \wr_pick$1692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + wire width 1 $1693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335" + cell $and $1694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -167871,64 +169417,92 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_SPR_spr1_o connect \B \wrpick_SPR_spr1_en_o - connect \Y $1367 + connect \Y $1693 end - process $group_466 - assign \wr_pick 1'0 - assign \wr_pick $1367 + process $group_541 + assign \wr_pick$1692 1'0 + assign \wr_pick$1692 $1693 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1369 + wire width 1 \wr_pick_dly$1695 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1369$next - process $group_467 - assign \wr_pick_dly$1369$next \wr_pick_dly$1369 - assign \wr_pick_dly$1369$next \wr_pick + wire width 1 \wr_pick_dly$1695$next + process $group_542 + assign \wr_pick_dly$1695$next \wr_pick_dly$1695 + assign \wr_pick_dly$1695$next \wr_pick$1692 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1369$next 1'0 + assign \wr_pick_dly$1695$next 1'0 end sync init - update \wr_pick_dly$1369 1'0 + update \wr_pick_dly$1695 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1369 \wr_pick_dly$1369$next + update \wr_pick_dly$1695 \wr_pick_dly$1695$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1370 + wire width 1 $1696 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1371 + cell $not $1697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1369 - connect \Y $1370 + connect \A \wr_pick_dly$1695 + connect \Y $1696 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1372 + wire width 1 $1698 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1373 + cell $and $1699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick - connect \B $1370 - connect \Y $1372 + connect \A \wr_pick$1692 + connect \B $1696 + connect \Y $1698 end - process $group_468 - assign \wr_pick_rise$819 1'0 - assign \wr_pick_rise$819 $1372 + process $group_543 + assign \wr_pick_rise$963 1'0 + assign \wr_pick_rise$963 $1698 sync init end - process $group_469 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 10 $1700 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + wire width 1 $1701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $and $1702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1692 + connect \B \wrpick_SPR_spr1_en_o + connect \Y $1701 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342" + cell $mux $1703 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B \pdecode2_spro + connect \S $1701 + connect \Y $1700 + end + process $group_544 + assign \write_en 10'0000000000 + assign \write_en $1700 + sync init + end + process $group_545 assign $memory_w_data 64'0000000000000000000000000000000000000000000000000000000000000000 assign $memory_w_data \fus_dest2_o$152 sync init end - process $group_470 + process $group_546 assign \coresync_rst 1'0 assign \coresync_rst \core_reset_i sync init