From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 07:26:20 +0000 (+0200)
Subject: Add InternalCellChecker support for $specify2 and $specify3
X-Git-Tag: yosys-0.9~141^2~19
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e1d73e03d38e9408cc7bce685645bb170ca5a6b8;p=yosys.git

Add InternalCellChecker support for $specify2 and $specify3

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 7d5334eb1..9e06b8323 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1194,13 +1194,27 @@ namespace {
 				return;
 			}
 
-			if (cell->type == "$specify2") {
-				// FIXME
-				return;
-			}
-
-			if (cell->type == "$specify3") {
-				// FIXME
+			if (cell->type.in("$specify2", "$specify3")) {
+				param_bool("\\FULL");
+				param_bool("\\SRC_DST_PEN");
+				param_bool("\\SRC_DST_POL");
+				param("\\T_RISE_MIN");
+				param("\\T_RISE_AVG");
+				param("\\T_RISE_MAX");
+				param("\\T_FALL_MIN");
+				param("\\T_FALL_AVG");
+				param("\\T_FALL_MAX");
+				port("\\EN", 1);
+				port("\\SRC", param("\\SRC_WIDTH"));
+				port("\\DST", param("\\DST_WIDTH"));
+				if (cell->type == "$specify3") {
+					param_bool("\\EDGE_EN");
+					param_bool("\\EDGE_POL");
+					param_bool("\\DAT_DST_PEN");
+					param_bool("\\DAT_DST_POL");
+					port("\\DAT", param("\\DST_WIDTH"));
+				}
+				check_expected();
 				return;
 			}