From: lkcl <lkcl@web>
Date: Mon, 28 Mar 2022 23:42:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2960
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e1eb5364630eb3e850004f740e595044c399b318;p=libreriscv.git

---

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 472ba5e1c..f52622b80 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -16,17 +16,18 @@ Condition Registers are conceptually perfect for use as predicate masks, the onl
 
 With the scalar OpenPOWER v3.0B ISA having already popcnt, cntlz and others normally seen in Vector Mask operations it makes sense to allow *both* scalar integers *and* CR-Vectors to be predicate masks.  That in turn means that much more comprehensive interaction between CRs and scalar Integers is required.
 
-The opportunity is therefore taken to also augment CR logical arithmetic as well, using a mask-based paradigm that takes into consideration multiple bits of each CR (eq/lt/gt/ov).  v3.0B Scalar CR instructions (crand, crxor) only allow a single bit calculation.
+The opportunity is therefore taken to also augment CR logical arithmetic as well, using a mask-based paradigm that takes into consideration multiple bits of each CR (eq/lt/gt/ov).  By contrast
+v3.0B Scalar CR instructions (crand, crxor) only allow a single bit calculation.
 
 Basic concept:
 
-* CR-based instructions that perform simple AND/OR/XOR from all four bits
-  of a CR to create a single bit value (0/1) in an integer register
+* CR-based instructions that perform simple AND/OR/XOR from any four bits
+  of a CR field to create a single bit value (0/1) in an integer register
 * Inverse of the same, taking a single bit value (0/1) from an integer
-  register to selectively target all four bits of a given CR
+  register to selectively target any four bits of a given CR Field
 * CR-to-CR version of the same, allowing multiple bits to be AND/OR/XORed
   in one hit.
-* Vectorisation of the same
+* Optional Vectorisation of the same when SVP64 is implemented
 
 Purpose:
 
@@ -134,7 +135,7 @@ bit 11=0, bit 19=0
     If Rc:
         CR0 = analyse(RT)
 
-This is a [[openpower/sv/normal]] SVP64 type operation and as
+When used with SVP64 Prefixing this is a [[openpower/sv/normal]] SVP64 type operation and as
 such can use Rc=1 and RC1 Data-dependent Mode capability
 
 **mtcrweird**
@@ -151,7 +152,7 @@ bit 11=1, bit 19=0
     n3 = mask[3] & (mode[3] == lsb)
     CR{BT} = n0 || n1 || n2 || n3
 
-This is a [[openpower/sv/cr_ops]] SVP64 type operation that has
+When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type operation that has
 3-bit Data-dependent and 3-bit Predicate-result capability
 (BT is 3 bits)
 
@@ -168,7 +169,7 @@ bit 11=0, bit 19=1
     n3 = mask[3] & (mode[3] == creg[3])
     CR{BT} = n0 || n1 || n2 || n3
 
-This is a [[openpower/sv/cr_ops]] SVP64 type operation that has
+When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type operation that has
 3-bit Data-dependent and 3-bit Predicate-result capability
 (BT is 3 bits)
 
@@ -188,7 +189,7 @@ bit 11=1, bit 19=1
     result = n0|n1|n2|n3 if M else n0&n1&n2&n3
     CR{BF}[bit] = result
 
-This is a [[openpower/sv/cr_ops]] SVP64 type operation that has
+When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type operation that has
 5-bit Data-dependent and 5-bit Predicate-result capability
 (BFT is 5 bits)