From: lkcl <lkcl@web>
Date: Fri, 6 May 2022 17:29:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2361
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e1ec501d1e5b8199b29c88446075065431faf8af;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 677651f86..de6a2eaa0 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -596,7 +596,7 @@ What the designers did however was not to add new Load-Store
 or Arithmetic instructions to RISC-V, but instead to "mark"
 registers with a tag.  These tags tell the CPU: when you are asked to
 carry out
-an add instruction on r6 and r7, do not take r6 or r7 from the reguster
+an add instruction on r6 and r7, do not take r6 or r7 from the register
 file, instead please perform a Cache-coherent Load-with-Increment
 on each, using special Address Registers for each.  Each new use
 of r6 therefore brings in an entirely new value *directly from