From: Alan Modra <amodra@gmail.com>
Date: Sat, 8 Feb 2020 00:44:54 +0000 (+1030)
Subject: z80 comments in archures.c
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e1f85e11f5875ac00a4b41f0ac45f1ba16fe5aed;p=binutils-gdb.git

z80 comments in archures.c

bfd-in2.h didn't match what was in archures.c and reloc.c.  This
fixes overlong comment lines and regenerates bfd-in2.h.

	* archures.c: Wrap overlong z80 comments.
	* bfd-in2.h: Regenerate.
---

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 96d8fe174a6..d176e95e000 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-10  Alan Modra  <amodra@gmail.com>
+
+	* archures.c: Wrap overlong z80 comments.
+	* bfd-in2.h: Regenerate.
+
 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 
 	PR 25469
diff --git a/bfd/archures.c b/bfd/archures.c
index 5789ea2afa5..885b027e434 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -504,15 +504,25 @@ DESCRIPTION
 .  bfd_arch_xtensa,    {* Tensilica's Xtensa cores.  *}
 .#define bfd_mach_xtensa	1
 .  bfd_arch_z80,
-.#define bfd_mach_z80strict	1 {* Zilog Z80 without undocumented opcodes.  *}
-.#define bfd_mach_z180		2 {* Zilog Z180: successor with additional instructions, but without halves of ix and iy *}
-.#define bfd_mach_z80		3 {* Zilog Z80 with ixl, ixh, iyl, and iyh.  *}
-.#define bfd_mach_ez80_z80	4 {* Zilog eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode *}
-.#define bfd_mach_ez80_adl	5 {* Zilog eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode *}
-.#define bfd_mach_z80n		6 {* Z80N *}
-.#define bfd_mach_z80full	7 {* Zilog Z80 with all undocumented instructions.  *}
-.#define bfd_mach_gbz80		8 {* GameBoy Z80 (reduced instruction set) *}
-.#define bfd_mach_r800		11 {* Ascii R800: successor with multiplication.  *}
+.{* Zilog Z80 without undocumented opcodes.  *}
+.#define bfd_mach_z80strict	1
+.{* Zilog Z180: successor with additional instructions, but without
+. halves of ix and iy.  *}
+.#define bfd_mach_z180		2
+.{* Zilog Z80 with ixl, ixh, iyl, and iyh.  *}
+.#define bfd_mach_z80		3
+.{* Zilog eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode.  *}
+.#define bfd_mach_ez80_z80	4
+.{* Zilog eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode.  *}
+.#define bfd_mach_ez80_adl	5
+.{* Z80N *}
+.#define bfd_mach_z80n		6
+.{* Zilog Z80 with all undocumented instructions.  *}
+.#define bfd_mach_z80full	7
+.{* GameBoy Z80 (reduced instruction set).  *}
+.#define bfd_mach_gbz80		8
+.{* ASCII R800: successor with multiplication.  *}
+.#define bfd_mach_r800		11
 .  bfd_arch_lm32,      {* Lattice Mico32.  *}
 .#define bfd_mach_lm32		1
 .  bfd_arch_microblaze,{* Xilinx MicroBlaze.  *}
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 180383be15b..6b30f5fbd80 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1897,15 +1897,25 @@ enum bfd_architecture
   bfd_arch_xtensa,    /* Tensilica's Xtensa cores.  */
 #define bfd_mach_xtensa        1
   bfd_arch_z80,
-#define bfd_mach_z80strict     1 /* Zilog Z80 without undocumented opcodes.  */
-#define bfd_mach_z180          2 /* Zilog Z180: successor with additional instructions, but without halves of ix and iy */
-#define bfd_mach_z80           3 /* Zilog Z80 with ixl, ixh, iyl, and iyh.  */
-#define bfd_mach_ez80_z80      4 /* Zilog eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode */
-#define bfd_mach_ez80_adl      5 /* Zilog eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode */
-#define bfd_mach_z80n          6 /* Z80N */
-#define bfd_mach_z80full       7 /* Zilog Z80 with all undocumented instructions.  */
-#define bfd_mach_gbz80         8 /* GameBoy Z80 (reduced instruction set) */
-#define bfd_mach_r800          11 /*Ascii R800: Z80 successor with multiplication.  */
+/* Zilog Z80 without undocumented opcodes.  */
+#define bfd_mach_z80strict     1
+/* Zilog Z180: successor with additional instructions, but without
+ halves of ix and iy.  */
+#define bfd_mach_z180          2
+/* Zilog Z80 with ixl, ixh, iyl, and iyh.  */
+#define bfd_mach_z80           3
+/* Zilog eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode.  */
+#define bfd_mach_ez80_z80      4
+/* Zilog eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode.  */
+#define bfd_mach_ez80_adl      5
+/* Z80N */
+#define bfd_mach_z80n          6
+/* Zilog Z80 with all undocumented instructions.  */
+#define bfd_mach_z80full       7
+/* GameBoy Z80 (reduced instruction set).  */
+#define bfd_mach_gbz80         8
+/* ASCII R800: successor with multiplication.  */
+#define bfd_mach_r800          11
   bfd_arch_lm32,      /* Lattice Mico32.  */
 #define bfd_mach_lm32          1
   bfd_arch_microblaze,/* Xilinx MicroBlaze.  */
@@ -5302,7 +5312,7 @@ BFD_RELOC_XTENSA_ASM_EXPAND.  */
 /* Highest 16 bits of multibyte (32 or 24 bit) value.  */
   BFD_RELOC_Z80_WORD1,
 
-/* 16 bit word big endian */
+/* Like BFD_RELOC_16 but big-endian.  */
   BFD_RELOC_Z80_16_BE,
 
 /* DJNZ offset.  */