From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Feb 2019 00:13:05 +0000 (+0000)
Subject: recompiled sfpy, testing FP16 again
X-Git-Tag: ls180-24jan2020~1800
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e209a4938625d7e0d43c4f477b824ef889999929;p=ieee754fpu.git

recompiled sfpy, testing FP16 again
---

diff --git a/src/add/test_add16.py b/src/add/test_add16.py
index e45ce359..4ee8428b 100644
--- a/src/add/test_add16.py
+++ b/src/add/test_add16.py
@@ -13,16 +13,16 @@ from unit_test_half import (get_mantissa, get_exponent, get_sign, is_nan,
                                 run_edge_cases, run_corner_cases)
 
 def testbench(dut):
-    yield from check_case(dut, 0x7800, 0xff6f, 0xff6f)
-    yield from check_case(dut, 0x0000, 0x7c32, 0x7e32)
-    yield from check_case(dut, 0x0000, 0x7da9, 0x7fa9)
-    yield from check_case(dut, 0x0000, 0x7ea0, 0x7ea0)
-    yield from check_case(dut, 0x7c9a, 0x8000, 0x7e9a)
-    yield from check_case(dut, 0x7d5e, 0x0000, 0x7f5e)
-    yield from check_case(dut, 0x8000, 0x7c8c, 0x7e8c)
-    yield from check_case(dut, 0x8000, 0xfc55, 0xfe55)
-    yield from check_case(dut, 0x8000, 0x7e1a, 0x7e1a)
-    yield from check_case(dut, 0xfc00, 0x7c00, 0xfe00)
+    #yield from check_case(dut, 0x7800, 0xff6f, 0xff6f)
+    #yield from check_case(dut, 0x0000, 0x7c32, 0x7e32)
+    #yield from check_case(dut, 0x0000, 0x7da9, 0x7fa9)
+    #yield from check_case(dut, 0x0000, 0x7ea0, 0x7ea0)
+    #yield from check_case(dut, 0x7c9a, 0x8000, 0x7e9a)
+    #yield from check_case(dut, 0x7d5e, 0x0000, 0x7f5e)
+    #yield from check_case(dut, 0x8000, 0x7c8c, 0x7e8c)
+    #yield from check_case(dut, 0x8000, 0xfc55, 0xfe55)
+    #yield from check_case(dut, 0x8000, 0x7e1a, 0x7e1a)
+    #yield from check_case(dut, 0xfc00, 0x7c00, 0xfe00)
     yield from check_case(dut, 0x8000, 0, 0)
     yield from check_case(dut, 0, 0, 0)
 
@@ -39,6 +39,6 @@ def testbench(dut):
     yield from run_edge_cases(dut, count, add)
 
 if __name__ == '__main__':
-    dut = FPADD(width=16, single_cycle=True)
+    dut = FPADD(width=16, single_cycle=False)
     run_simulation(dut, testbench(dut), vcd_name="test_add16.vcd")