From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 2 Apr 2014 19:06:55 +0000 (+0200)
Subject: Added SIMLIB_NOSR to simlib.v
X-Git-Tag: yosys-0.3.0~32
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e24797add0ceb0e8c3571cec9351a2b0120e9b19;p=yosys.git

Added SIMLIB_NOSR to simlib.v
---

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 908314f84..16e6a1b21 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -977,6 +977,7 @@ end
 endmodule
 
 // --------------------------------------------------------
+`ifndef SIMLIB_NOSR
 
 module \$sr (SET, CLR, Q);
 
@@ -1003,6 +1004,7 @@ endgenerate
 
 endmodule
 
+`endif
 // --------------------------------------------------------
 
 module \$dff (CLK, D, Q);
@@ -1022,6 +1024,7 @@ end
 endmodule
 
 // --------------------------------------------------------
+`ifndef SIMLIB_NOSR
 
 module \$dffsr (CLK, SET, CLR, D, Q);
 
@@ -1053,6 +1056,7 @@ endgenerate
 
 endmodule
 
+`endif
 // --------------------------------------------------------
 
 module \$adff (CLK, ARST, D, Q);
@@ -1096,6 +1100,7 @@ end
 endmodule
 
 // --------------------------------------------------------
+`ifndef SIMLIB_NOSR
 
 module \$dlatchsr (EN, SET, CLR, D, Q);
 
@@ -1127,6 +1132,7 @@ endgenerate
 
 endmodule
 
+`endif
 // --------------------------------------------------------
 
 module \$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);