From: lkcl <lkcl@web>
Date: Thu, 16 Sep 2021 10:38:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~103
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e25098f94cb0251f1fd3aee0f7977f28ced6c687;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 7ea6676aa..3bad3493c 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -257,16 +257,11 @@ or in the case of divide, to get better accuracy, to perform a multiply
 cascade followed by a final divide.
 
 Note that single-operand or three-operand scalar-dest reduce is perfectly
-well permitted: both still meet the qualifying characteristics that one
-source operand can also be the destination, which allows the "accumulator"
-to be identified.
-
-If the "accumulator" cannot be identified (one of the sources is also
-a destination) the results are **UNDEFINED**.  This permits implementations
-to not have to have complex decoding analysis of register fields: it
-is thus up to the programmer to ensure that one of the source registers
-is also a destination register in order to take advantage of Scalar
-Reduce Mode.
+well permitted: the programmer may still declare one register, used as
+both a Vector source and Scalar destination, to be utilised as 
+the "accumulator".  In the case of `sv.fmadds` and `sv.maddhw` etc
+this naturally fits well with the normal expected usage of these
+operations.
 
 If an interrupt or exception occurs in the middle of the scalar mapreduce,
 the scalar destination register **MUST** be updated with the current
@@ -281,13 +276,6 @@ parallel optimisation of the scalar reduce operation: it's just that
 as far as the user is concerned, all exceptions and interrupts **MUST**
 be precise.
 
-It is also possible, using this mode, to perform iterative computations.
-Setting the source register to be one greater or one less than the
-destination will result in a cumulative cascade of element-based
-operations being issued to the underlying hardware, where standard
-Register Hazard observance is expected and required.  "Reverse Gear"
-may prove useful in some circumstances.
-
 ## Vector result reduce mode
 
 Vector result reduce mode may utilise the destination vector for