From: lkcl <lkcl@web>
Date: Tue, 29 Mar 2022 06:02:13 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2953
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e266171b2317ab59b289e9d7d3af2db0d4b3faee;p=libreriscv.git

---

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 8baa3a2ef..14ce3e208 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -68,11 +68,11 @@ Instruction format:
 
 |0-5|6-10 |11|12-15|16-18|19-20|21-25  |26-30  |31|name      |
 |---|---- |--|-----|-----|-----|-----  |-----  |--|----      |
-|19 |RT   |  |mask |BB   |     |XO[0:4]|XO[5:9]|/ |          |
-|19 |RT   |M |mask |BB   | 0 0 |XO[0:4]|0 mode |Rc|crrweird  |
-|19 |RA   |/ |mask |BT   | 0 1 |XO[0:4]|0 mode |/ |mtcrweird |
-|19 |BT //|M |mask |BB   | 1 0 |XO[0:4]|0 mode |/ |crweird   |
-|19 |BFT  |/ |mask |BB   | 1 1 |XO[0:4]|0 mode |/ |crweirder |
+|19 |RT   |  |mask |BFA  |     |XO[0:4]|XO[5:9]|/ |          |
+|19 |RT   |M |mask |BFA  | 0 0 |XO[0:4]|0 mode |Rc|crrweird  |
+|19 |RA   |/ |mask |BF   | 0 1 |XO[0:4]|0 mode |/ |mtcrweird |
+|19 |BFT//|M |mask |BFA  | 1 0 |XO[0:4]|0 mode |/ |crweird   |
+|19 |BF   |/ |mask |BFA  | 1 1 |XO[0:4]|0 mode |/ |crweirder |
 
 **crrweird**
 
@@ -80,9 +80,9 @@ mode is encoded in XO and is 4 bits
 
 bit 19=0, bit 20=0
 
-    crrweird: RT, BB, mask.mode
+    crrweird: RT, BFA, mask.mode
 
-    creg = CR{BB}
+    creg = CR{BFA}
     n0 = mask[0] & (mode[0] == creg[0])
     n1 = mask[1] & (mode[1] == creg[1])
     n2 = mask[2] & (mode[2] == creg[2])
@@ -99,7 +99,7 @@ such can use Rc=1 and RC1 Data-dependent Mode capability
 
 bit 19=0, bit 20=1
 
-    mtcrweird: BT, RA, mask.mode
+    mtcrweird: BF, RA, mask.mode
 
     reg = (RA|0)
     lsb = reg[63] # MSB0 numbering
@@ -107,7 +107,7 @@ bit 19=0, bit 20=1
     n1 = mask[1] & (mode[1] == lsb)
     n2 = mask[2] & (mode[2] == lsb)
     n3 = mask[3] & (mode[3] == lsb)
-    CR{BT} = n0 || n1 || n2 || n3
+    CR{BF} = n0 || n1 || n2 || n3
 
 When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type operation that has
 3-bit Data-dependent and 3-bit Predicate-result capability
@@ -117,14 +117,14 @@ When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type oper
 
 bit 19=1, bit 20=0
 
-    crweird: BT, BB, mask.mode
+    crweird: BF, BFA, mask.mode
 
-    creg = CR{BB}
+    creg = CR{BFA}
     n0 = mask[0] & (mode[0] == creg[0])
     n1 = mask[1] & (mode[1] == creg[1])
     n2 = mask[2] & (mode[2] == creg[2])
     n3 = mask[3] & (mode[3] == creg[3])
-    CR{BT} = n0 || n1 || n2 || n3
+    CR{BF} = n0 || n1 || n2 || n3
 
 When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type operation that has
 3-bit Data-dependent and 3-bit Predicate-result capability
@@ -134,15 +134,15 @@ When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type oper
 
 bit 19=1, bit 20=1
 
-    crweirder: BFT, BB, mask.mode
+    crweirder: BT, BFA, mask.mode
 
-    creg = CR{BB}
+    creg = CR{BFA}
     n0 = mask[0] & (mode[0] == creg[0])
     n1 = mask[1] & (mode[1] == creg[1])
     n2 = mask[2] & (mode[2] == creg[2])
     n3 = mask[3] & (mode[3] == creg[3])
-    BF = BFT[2:4] # select CR
-    bit = BFT[0:1] # select bit of CR
+    BF = BT[2:4] # select CR
+    bit = BT[0:1] # select bit of CR
     result = n0|n1|n2|n3 if M else n0&n1&n2&n3
     CR{BF}[bit] = result
 
@@ -152,9 +152,9 @@ When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type oper
 
 **Example Pseudo-ops:**
 
-    mtcri BB, mode    mtcrweird r0, BB, 0b1111.~mode
-    mtcrset BB, mask  mtcrweird r0, BB, mask.0b0000
-    mtcrclr BB, mask  mtcrweird r0, BB, mask.0b1111
+    mtcri BFA, mode    mtcrweird r0, BFA, 0b1111.~mode
+    mtcrset BFA, mask  mtcrweird r0, BFA, mask.0b0000
+    mtcrclr BFA, mask  mtcrweird r0, BFA, mask.0b1111
 
 # Vectorised versions