From: lkcl <lkcl@web>
Date: Wed, 22 Sep 2021 16:05:19 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~40
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e26fd23765e713734e5ae7f3bcd3e816b4bdaf61;p=libreriscv.git

---

diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn
index b86d6d76a..b87847b6e 100644
--- a/HDL_workflow.mdwn
+++ b/HDL_workflow.mdwn
@@ -543,7 +543,9 @@ See [[HDL_workflow/coriolis2]] page, for those people doing layout work.
 
 A portable FPGA place and route tool.
 
-See [[HDL_workflow/nextpnr]] page for installation instructions of nextpnr with ECP5 support for Lattice FPGA ECP5 series.
+See [[HDL_workflow/nextpnr]] page for installation instructions of nextpnr with ECP5 support for Lattice FPGA ECP5 series.  Also see
+[[HDL_workflow/ECP5_FPGA]] for connecting up to JTAG with a ULX3S
+and the Lattice VERSA_ECP5.
 
 ## Verilator