From: Mikhail Maltsev Date: Fri, 30 Oct 2015 04:08:15 +0000 (+0000) Subject: [PATCH 8/9] ENABLE_CHECKING refactoring: target-specific parts X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e28c20522742a9782f6468551f11e3266ea2f823;p=gcc.git [PATCH 8/9] ENABLE_CHECKING refactoring: target-specific parts * config/alpha/alpha.c (alpha_function_arg): Use gcc_checking_assert, flag_checking and/or CHECKING_P to eliminate conditional compilation on ENABLE_CHECKING. * config/arm/arm.c (arm_unwind_emit_sequence): Likewise. * config/bfin/bfin.c (hwloop_optimize): Likewise. * config/i386/i386.c (ix86_print_operand_address): Likewise. (output_387_binary_op): Likewise. * config/ia64/ia64.c (ia64_sched_init, bundling): Likewise. * config/m68k/m68k.c (m68k_sched_md_init_global): Likewise. * config/rs6000/rs6000.c (htm_expand_builtin, rs6000_emit_prologue): Likewise. * config/rs6000/rs6000.h: Likewise. * config/visium/visium.c (visium_setup_incoming_varargs): Likewise. From-SVN: r229567 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c9250b658ab..934711b183b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2015-10-29 Mikhail Maltsev + + * config/alpha/alpha.c (alpha_function_arg): Use gcc_checking_assert, + flag_checking and/or CHECKING_P to eliminate conditional compilation + on ENABLE_CHECKING. + * config/arm/arm.c (arm_unwind_emit_sequence): Likewise. + * config/bfin/bfin.c (hwloop_optimize): Likewise. + * config/i386/i386.c (ix86_print_operand_address): Likewise. + (output_387_binary_op): Likewise. + * config/ia64/ia64.c (ia64_sched_init, bundling): Likewise. + * config/m68k/m68k.c (m68k_sched_md_init_global): Likewise. + * config/rs6000/rs6000.c (htm_expand_builtin, rs6000_emit_prologue): + Likewise. + * config/rs6000/rs6000.h: Likewise. + * config/visium/visium.c (visium_setup_incoming_varargs): Likewise. + 2015-10-29 Kaz Kojima * config/sh/sh.opt (mfdpic): Add missing period. diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index d22bf67e52b..11da372fce7 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -5558,11 +5558,9 @@ alpha_function_arg (cumulative_args_t cum_v, machine_mode mode, basereg = 16; else { -#ifdef ENABLE_CHECKING /* With alpha_split_complex_arg, we shouldn't see any raw complex values here. */ - gcc_assert (!COMPLEX_MODE_P (mode)); -#endif + gcc_checking_assert (!COMPLEX_MODE_P (mode)); /* Set up defaults for FP operands passed in FP registers, and integral operands passed in integer registers. */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index a598c84392d..7c72a81ece0 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -26857,20 +26857,21 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) else asm_fprintf (asm_out_file, "%r", reg); -#ifdef ENABLE_CHECKING - /* Check that the addresses are consecutive. */ - e = XEXP (SET_DEST (e), 0); - if (GET_CODE (e) == PLUS) - gcc_assert (REG_P (XEXP (e, 0)) - && REGNO (XEXP (e, 0)) == SP_REGNUM - && CONST_INT_P (XEXP (e, 1)) - && offset == INTVAL (XEXP (e, 1))); - else - gcc_assert (i == 1 - && REG_P (e) - && REGNO (e) == SP_REGNUM); - offset += reg_size; -#endif + if (flag_checking) + { + /* Check that the addresses are consecutive. */ + e = XEXP (SET_DEST (e), 0); + if (GET_CODE (e) == PLUS) + gcc_assert (REG_P (XEXP (e, 0)) + && REGNO (XEXP (e, 0)) == SP_REGNUM + && CONST_INT_P (XEXP (e, 1)) + && offset == INTVAL (XEXP (e, 1))); + else + gcc_assert (i == 1 + && REG_P (e) + && REGNO (e) == SP_REGNUM); + offset += reg_size; + } } fprintf (asm_out_file, "}\n"); if (padfirst) diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c index 7334a52075c..6a5f90a7f1e 100644 --- a/gcc/config/bfin/bfin.c +++ b/gcc/config/bfin/bfin.c @@ -3792,8 +3792,7 @@ hwloop_optimize (hwloop_info loop) edge e; edge_iterator ei; -#ifdef ENABLE_CHECKING - if (loop->head != loop->incoming_dest) + if (flag_checking && loop->head != loop->incoming_dest) { /* We aren't entering the loop at the top. Since we've established that the loop is entered only at one point, this means there @@ -3803,7 +3802,6 @@ hwloop_optimize (hwloop_info loop) FOR_EACH_EDGE (e, ei, loop->head->preds) gcc_assert (!(e->flags & EDGE_FALLTHRU)); } -#endif emit_insn_before (seq, BB_HEAD (loop->head)); seq = emit_label_before (gen_label_rtx (), seq); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 8476677f1c1..913dc00e02c 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -17348,22 +17348,23 @@ ix86_print_operand_address (FILE *file, rtx addr) /* Print SImode register names to force addr32 prefix. */ if (SImode_address_operand (addr, VOIDmode)) { -#ifdef ENABLE_CHECKING - gcc_assert (TARGET_64BIT); - switch (GET_CODE (addr)) + if (flag_checking) { - case SUBREG: - gcc_assert (GET_MODE (addr) == SImode); - gcc_assert (GET_MODE (SUBREG_REG (addr)) == DImode); - break; - case ZERO_EXTEND: - case AND: - gcc_assert (GET_MODE (addr) == DImode); - break; - default: - gcc_unreachable (); + gcc_assert (TARGET_64BIT); + switch (GET_CODE (addr)) + { + case SUBREG: + gcc_assert (GET_MODE (addr) == SImode); + gcc_assert (GET_MODE (SUBREG_REG (addr)) == DImode); + break; + case ZERO_EXTEND: + case AND: + gcc_assert (GET_MODE (addr) == DImode); + break; + default: + gcc_unreachable (); + } } -#endif gcc_assert (!code); code = 'k'; } @@ -17620,10 +17621,10 @@ output_387_binary_op (rtx insn, rtx *operands) const char *ssep; int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]); -#ifdef ENABLE_CHECKING /* Even if we do not want to check the inputs, this documents input constraints. Which helps in understanding the following code. */ - if (STACK_REG_P (operands[0]) + if (flag_checking + && STACK_REG_P (operands[0]) && ((REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]) && (STACK_REG_P (operands[2]) || MEM_P (operands[2]))) @@ -17633,8 +17634,7 @@ output_387_binary_op (rtx insn, rtx *operands) && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2]))) ; /* ok */ else - gcc_assert (is_sse); -#endif + gcc_checking_assert (is_sse); switch (GET_CODE (operands[3])) { diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index 879113895f3..d92af177082 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -6125,7 +6125,7 @@ struct reg_write_state /* Cumulative info for the current instruction group. */ struct reg_write_state rws_sum[NUM_REGS]; -#ifdef ENABLE_CHECKING +#if CHECKING_P /* Bitmap whether a register has been written in the current insn. */ HARD_REG_ELT_TYPE rws_insn[(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1) / HOST_BITS_PER_WIDEST_FAST_INT]; @@ -7293,15 +7293,13 @@ ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose ATTRIBUTE_UNUSED, int max_ready ATTRIBUTE_UNUSED) { -#ifdef ENABLE_CHECKING - rtx_insn *insn; - - if (!sel_sched_p () && reload_completed) - for (insn = NEXT_INSN (current_sched_info->prev_head); - insn != current_sched_info->next_tail; - insn = NEXT_INSN (insn)) - gcc_assert (!SCHED_GROUP_P (insn)); -#endif + if (flag_checking && !sel_sched_p () && reload_completed) + { + for (rtx_insn *insn = NEXT_INSN (current_sched_info->prev_head); + insn != current_sched_info->next_tail; + insn = NEXT_INSN (insn)) + gcc_assert (!SCHED_GROUP_P (insn)); + } last_scheduled_insn = NULL; init_insn_group_barriers (); @@ -9299,54 +9297,52 @@ bundling (FILE *dump, int verbose, rtx_insn *prev_head_insn, rtx_insn *tail) } } -#ifdef ENABLE_CHECKING - { - /* Assert right calculation of middle_bundle_stops. */ - int num = best_state->middle_bundle_stops; - bool start_bundle = true, end_bundle = false; - - for (insn = NEXT_INSN (prev_head_insn); - insn && insn != tail; - insn = NEXT_INSN (insn)) - { - if (!INSN_P (insn)) - continue; - if (recog_memoized (insn) == CODE_FOR_bundle_selector) - start_bundle = true; - else - { - rtx_insn *next_insn; - - for (next_insn = NEXT_INSN (insn); - next_insn && next_insn != tail; - next_insn = NEXT_INSN (next_insn)) - if (INSN_P (next_insn) - && (ia64_safe_itanium_class (next_insn) - != ITANIUM_CLASS_IGNORE - || recog_memoized (next_insn) - == CODE_FOR_bundle_selector) - && GET_CODE (PATTERN (next_insn)) != USE - && GET_CODE (PATTERN (next_insn)) != CLOBBER) - break; + if (flag_checking) + { + /* Assert right calculation of middle_bundle_stops. */ + int num = best_state->middle_bundle_stops; + bool start_bundle = true, end_bundle = false; - end_bundle = next_insn == NULL_RTX - || next_insn == tail - || (INSN_P (next_insn) - && recog_memoized (next_insn) - == CODE_FOR_bundle_selector); - if (recog_memoized (insn) == CODE_FOR_insn_group_barrier - && !start_bundle && !end_bundle - && next_insn - && !unknown_for_bundling_p (next_insn)) - num--; - - start_bundle = false; - } - } + for (insn = NEXT_INSN (prev_head_insn); + insn && insn != tail; + insn = NEXT_INSN (insn)) + { + if (!INSN_P (insn)) + continue; + if (recog_memoized (insn) == CODE_FOR_bundle_selector) + start_bundle = true; + else + { + rtx_insn *next_insn; + + for (next_insn = NEXT_INSN (insn); + next_insn && next_insn != tail; + next_insn = NEXT_INSN (next_insn)) + if (INSN_P (next_insn) + && (ia64_safe_itanium_class (next_insn) + != ITANIUM_CLASS_IGNORE + || recog_memoized (next_insn) + == CODE_FOR_bundle_selector) + && GET_CODE (PATTERN (next_insn)) != USE + && GET_CODE (PATTERN (next_insn)) != CLOBBER) + break; + + end_bundle = next_insn == NULL_RTX + || next_insn == tail + || (INSN_P (next_insn) + && recog_memoized (next_insn) == CODE_FOR_bundle_selector); + if (recog_memoized (insn) == CODE_FOR_insn_group_barrier + && !start_bundle && !end_bundle + && next_insn + && !unknown_for_bundling_p (next_insn)) + num--; + + start_bundle = false; + } + } - gcc_assert (num == 0); - } -#endif + gcc_assert (num == 0); + } free (index_to_bundle_states); finish_bundle_state_table (); diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index bfc19f30eb4..37b1af2db3a 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -6118,28 +6118,27 @@ m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED, int sched_verbose ATTRIBUTE_UNUSED, int n_insns ATTRIBUTE_UNUSED) { -#ifdef ENABLE_CHECKING /* Check that all instructions have DFA reservations and that all instructions can be issued from a clean state. */ - { - rtx_insn *insn; - state_t state; + if (flag_checking) + { + rtx_insn *insn; + state_t state; - state = alloca (state_size ()); + state = alloca (state_size ()); - for (insn = get_insns (); insn != NULL; insn = NEXT_INSN (insn)) - { - if (INSN_P (insn) && recog_memoized (insn) >= 0) - { - gcc_assert (insn_has_dfa_reservation_p (insn)); + for (insn = get_insns (); insn != NULL; insn = NEXT_INSN (insn)) + { + if (INSN_P (insn) && recog_memoized (insn) >= 0) + { + gcc_assert (insn_has_dfa_reservation_p (insn)); - state_reset (state); - if (state_transition (state, insn) >= 0) - gcc_unreachable (); - } - } - } -#endif + state_reset (state); + if (state_transition (state, insn) >= 0) + gcc_unreachable (); + } + } + } /* Setup target cpu. */ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index bbdd1425eeb..53b86afd83f 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -12906,15 +12906,13 @@ htm_expand_builtin (tree exp, rtx target, bool * expandedp) case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */ case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */ op[nopnds++] = GEN_INT (1); -#ifdef ENABLE_CHECKING - attr |= RS6000_BTC_UNARY; -#endif + if (flag_checking) + attr |= RS6000_BTC_UNARY; break; case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */ op[nopnds++] = GEN_INT (0); -#ifdef ENABLE_CHECKING - attr |= RS6000_BTC_UNARY; -#endif + if (flag_checking) + attr |= RS6000_BTC_UNARY; break; default: break; @@ -12935,21 +12933,23 @@ htm_expand_builtin (tree exp, rtx target, bool * expandedp) op[nopnds++] = cr; } -#ifdef ENABLE_CHECKING - int expected_nopnds = 0; - if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY) - expected_nopnds = 1; - else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY) - expected_nopnds = 2; - else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY) - expected_nopnds = 3; - if (!(attr & RS6000_BTC_VOID)) - expected_nopnds += 1; - if (uses_spr) - expected_nopnds += 2; + if (flag_checking) + { + int expected_nopnds = 0; + if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY) + expected_nopnds = 1; + else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY) + expected_nopnds = 2; + else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY) + expected_nopnds = 3; + if (!(attr & RS6000_BTC_VOID)) + expected_nopnds += 1; + if (uses_spr) + expected_nopnds += 2; - gcc_assert (nopnds == expected_nopnds && nopnds <= MAX_HTM_OPERANDS); -#endif + gcc_assert (nopnds == expected_nopnds + && nopnds <= MAX_HTM_OPERANDS); + } switch (nopnds) { @@ -24325,7 +24325,7 @@ rs6000_emit_prologue (void) prior to it, when r12 is not used here for other purposes. */ rtx_insn *sp_adjust = 0; -#ifdef ENABLE_CHECKING +#if CHECKING_P /* Track and check usage of r0, r11, r12. */ int reg_inuse = using_static_chain_p ? 1 << 11 : 0; #define START_USE(R) do \ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index cad1551a15c..02da097227b 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1479,15 +1479,10 @@ enum reg_class extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; -#if ENABLE_CHECKING #define REGNO_REG_CLASS(REGNO) \ - (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \ + (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ rs6000_regno_regclass[(REGNO)]) -#else -#define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)] -#endif - /* Register classes for various constraints that are based on the target switches. */ enum r6000_reg_class_enum { diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c index 5e7b944ec74..d1b580ebc44 100644 --- a/gcc/config/visium/visium.c +++ b/gcc/config/visium/visium.c @@ -1338,7 +1338,7 @@ visium_setup_incoming_varargs (cumulative_args_t pcum_v, local_args_so_far.p = &local_copy; locargs = get_cumulative_args (pcum_v); -#ifdef ENABLE_CHECKING +#if CHECKING_P local_args_so_far.magic = CUMULATIVE_ARGS_MAGIC; #endif