From: lkcl <lkcl@web>
Date: Wed, 8 Sep 2021 12:47:57 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~181
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e295b94ea8daecdb4677d810dca5eca9f7d563dd;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 43ba20158..9affbc5ff 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -4,7 +4,8 @@ Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, particularly with respect to element
 width (which is clearly meaningless). Likewise, arithmetic saturation
 (an important part of Arithmetic SVP64)
-has no meaning. Consequently an alternative Mode Format is required.
+has no meaning. Additionally, extra modes are required that only make
+sense for Vectorised CR Operations. Consequently an alternative Mode Format is required.
 
 This alternative mapping **only** applies to instructions that **only**
 reference a CR Field or CR bit as the sole exclusive result. This section