From: lkcl <lkcl@web>
Date: Tue, 14 Sep 2021 13:06:03 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~146
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e2ade9487a845a41f3ced65fe699fd6285bea495;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 439392b2d..ccdbec5e8 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -157,13 +157,10 @@ Brief description of fields:
   This is identical behaviour to how programming languages perform
   early-exit on Boolean Logic chains.
 * **VLI** VLSET is identical to Data-dependent Fail-First mode.
-  In VLSET mode, VL is set equal (truncated) to the first point
-  where, assuming Conditions are tested sequentially, the branch
-  proceeds
-  *or does not take place* depending if VSb is set.
+  In VLSET mode, VL *may* (depending on `VSb`) be truncated.
   If VLI (Vector Length Inclusive) is clear,
   VL is truncated to *exclude* the current element, otherwise it is
-  included. SVSTATE.MVL is not changed: only VL.
+  included. SVSTATE.MVL is not altered: only VL.
 * **LRu**: Link Register Update. When set, Link Register will
   only be updated if the Branch Condition succeeds. This avoids
   destruction of LR during loops (particularly Vertical-First