From: Luke Kenneth Casson Leighton Date: Tue, 2 Jun 2020 13:54:51 +0000 (+0100) Subject: rename regspecs to give a consistent naming scheme X-Git-Tag: div_pipeline~657 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e2b26c520cf2e1734123332191b0f7d53fc5cf6e;p=soc.git rename regspecs to give a consistent naming scheme the Decode phase needs to be able to associate regspec information with actual signals, back in Decode2Execute1Type. the simplest way to do this is to make the regspec register names consistent and actually refer *to* Decode2Execute1Type signals --- diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py index 33f54b02..b9423944 100644 --- a/src/soc/fu/alu/pipe_data.py +++ b/src/soc/fu/alu/pipe_data.py @@ -6,50 +6,54 @@ from soc.decoder.power_decoder2 import Data class ALUInputData(IntegerData): - regspec = [('INT', 'a', '0:63'), - ('INT', 'b', '0:63'), + regspec = [('INT', 'ra', '0:63'), + ('INT', 'rb', '0:63'), ('XER', 'xer_so', '32'), ('XER', 'xer_ca', '34,45')] def __init__(self, pspec): super().__init__(pspec) - self.a = Signal(64, reset_less=True) # RA - self.b = Signal(64, reset_less=True) # RB/immediate + self.ra = Signal(64, reset_less=True) # RA + self.rb = Signal(64, reset_less=True) # RB/immediate self.xer_so = Signal(reset_less=True) # XER bit 32: SO self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32 + # convenience + self.a, self.b = self.ra, self.rb def __iter__(self): yield from super().__iter__() - yield self.a - yield self.b + yield self.ra + yield self.rb yield self.xer_ca yield self.xer_so def eq(self, i): lst = super().eq(i) - return lst + [self.a.eq(i.a), self.b.eq(i.b), + return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb), self.xer_ca.eq(i.xer_ca), self.xer_so.eq(i.xer_so)] class ALUOutputData(IntegerData): regspec = [('INT', 'o', '0:63'), - ('CR', 'cr0', '0:3'), + ('CR', 'cr_a', '0:3'), ('XER', 'xer_ca', '34,45'), ('XER', 'xer_ov', '33,44'), ('XER', 'xer_so', '32')] def __init__(self, pspec): super().__init__(pspec) self.o = Data(64, name="stage_o") - self.cr0 = Data(4, name="cr0") + self.cr_a = Data(4, name="cr_a") self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32 self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32 self.xer_so = Data(1, name="xer_so") + # convenience + self.cr0 = self.cr_a def __iter__(self): yield from super().__iter__() yield self.o yield self.xer_ca - yield self.cr0 + yield self.cr_a yield self.xer_ov yield self.xer_so @@ -57,7 +61,7 @@ class ALUOutputData(IntegerData): lst = super().eq(i) return lst + [self.o.eq(i.o), self.xer_ca.eq(i.xer_ca), - self.cr0.eq(i.cr0), + self.cr_a.eq(i.cr_a), self.xer_ov.eq(i.xer_ov), self.xer_so.eq(i.xer_so)] diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py index a71c9dd1..40633d6d 100644 --- a/src/soc/fu/branch/pipe_data.py +++ b/src/soc/fu/branch/pipe_data.py @@ -33,8 +33,8 @@ from soc.fu.branch.br_input_record import CompBROpSubset # TODO: replace class BranchInputData(IntegerData): regspec = [('SPR', 'spr1', '0:63'), ('SPR', 'spr2', '0:63'), - ('CR', 'cr', '0:3'), - ('PC', 'cia', '0:63')] + ('CR', 'cr_a', '0:3'), + ('FAST', 'cia', '0:63')] def __init__(self, pspec): super().__init__(pspec) # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR @@ -43,30 +43,31 @@ class BranchInputData(IntegerData): self.spr1 = Signal(64, reset_less=True) # see table above, SPR1 self.spr2 = Signal(64, reset_less=True) # see table above, SPR2 - self.cr = Signal(4, reset_less=True) # Condition Register(s) CR0-7 + self.cr_a = Signal(4, reset_less=True) # Condition Register(s) CR0-7 self.cia = Signal(64, reset_less=True) # Current Instruction Address # convenience variables. not all of these are used at once self.ctr = self.srr0 = self.hsrr0 = self.spr1 self.lr = self.tar = self.srr1 = self.hsrr1 = self.spr2 + self.cr = self.cr_a def __iter__(self): yield from super().__iter__() yield self.spr1 yield self.spr2 - yield self.cr + yield self.cr_a yield self.cia def eq(self, i): lst = super().eq(i) return lst + [self.spr1.eq(i.spr1), self.spr2.eq(i.spr2), - self.cr.eq(i.cr), self.cia.eq(i.cia)] + self.cr_a.eq(i.cr_a), self.cia.eq(i.cia)] class BranchOutputData(IntegerData): regspec = [('SPR', 'spr1', '0:63'), ('SPR', 'spr2', '0:63'), - ('PC', 'nia', '0:63')] + ('FAST', 'nia', '0:63')] def __init__(self, pspec): super().__init__(pspec) self.spr1 = Data(64, name="spr1") diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py index 0c7b0623..12475250 100644 --- a/src/soc/fu/compunits/test/test_alu_compunit.py +++ b/src/soc/fu/compunits/test/test_alu_compunit.py @@ -23,13 +23,13 @@ class ALUTestRunner(TestRunner): reg1_ok = yield dec2.e.read_reg1.ok if reg1_ok: data1 = yield dec2.e.read_reg1.data - res['a'] = sim.gpr(data1).value + res['ra'] = sim.gpr(data1).value # RB (or immediate) reg2_ok = yield dec2.e.read_reg2.ok if reg2_ok: data2 = yield dec2.e.read_reg2.data - res['b'] = sim.gpr(data2).value + res['rb'] = sim.gpr(data2).value # XER.ca carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0 @@ -69,7 +69,7 @@ class ALUTestRunner(TestRunner): # CR (CR0-7) if cridx_ok: cr_expected = sim.crl[cridx].get_range().value - cr_actual = res['cr0'] + cr_actual = res['cr_a'] print ("CR", cridx, cr_expected, cr_actual) self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code)) diff --git a/src/soc/fu/compunits/test/test_cr_compunit.py b/src/soc/fu/compunits/test/test_cr_compunit.py index cf8572e9..5d502f9f 100644 --- a/src/soc/fu/compunits/test/test_cr_compunit.py +++ b/src/soc/fu/compunits/test/test_cr_compunit.py @@ -45,13 +45,13 @@ class CRTestRunner(TestRunner): reg1_ok = yield dec2.e.read_reg1.ok if reg1_ok: data1 = yield dec2.e.read_reg1.data - res['a'] = sim.gpr(data1).value + res['ra'] = sim.gpr(data1).value # RB (or immediate) reg2_ok = yield dec2.e.read_reg2.ok if reg2_ok: data2 = yield dec2.e.read_reg2.data - res['b'] = sim.gpr(data2).value + res['rb'] = sim.gpr(data2).value print ("get inputs", res) return res @@ -75,7 +75,7 @@ class CRTestRunner(TestRunner): if cr_en: cr_sel = yield dec2.e.write_cr.data expected_cr = sim.crl[cr_sel].get_range().value - real_cr = res['cr'] + real_cr = res['cr_a'] self.assertEqual(expected_cr, real_cr, code) # RT diff --git a/src/soc/fu/compunits/test/test_logical_compunit.py b/src/soc/fu/compunits/test/test_logical_compunit.py index 0ba7e8d9..8745b0b1 100644 --- a/src/soc/fu/compunits/test/test_logical_compunit.py +++ b/src/soc/fu/compunits/test/test_logical_compunit.py @@ -23,13 +23,13 @@ class LogicalTestRunner(TestRunner): reg1_ok = yield dec2.e.read_reg1.ok if reg1_ok: data1 = yield dec2.e.read_reg1.data - res['a'] = sim.gpr(data1).value + res['ra'] = sim.gpr(data1).value # RB (or immediate) reg2_ok = yield dec2.e.read_reg2.ok if reg2_ok: data2 = yield dec2.e.read_reg2.data - res['b'] = sim.gpr(data2).value + res['rb'] = sim.gpr(data2).value return res @@ -60,7 +60,7 @@ class LogicalTestRunner(TestRunner): # CR (CR0-7) if cridx_ok: cr_expected = sim.crl[cridx].get_range().value - cr_actual = res['cr0'] + cr_actual = res['cr_a'] print ("CR", cridx, cr_expected, cr_actual) self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code)) diff --git a/src/soc/fu/compunits/test/test_shiftrot_compunit.py b/src/soc/fu/compunits/test/test_shiftrot_compunit.py index 603b3fbb..aeb7de8b 100644 --- a/src/soc/fu/compunits/test/test_shiftrot_compunit.py +++ b/src/soc/fu/compunits/test/test_shiftrot_compunit.py @@ -23,7 +23,7 @@ class ShiftRotTestRunner(TestRunner): reg1_ok = yield dec2.e.read_reg1.ok if reg1_ok: data1 = yield dec2.e.read_reg1.data - res['a'] = sim.gpr(data1).value + res['ra'] = sim.gpr(data1).value # RB reg2_ok = yield dec2.e.read_reg2.ok @@ -35,7 +35,7 @@ class ShiftRotTestRunner(TestRunner): reg3_ok = yield dec2.e.read_reg3.ok if reg3_ok: data3 = yield dec2.e.read_reg3.data - res['rs'] = sim.gpr(data3).value + res['rc'] = sim.gpr(data3).value # XER.ca carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0 @@ -75,7 +75,7 @@ class ShiftRotTestRunner(TestRunner): # CR (CR0-7) if cridx_ok: cr_expected = sim.crl[cridx].get_range().value - cr_actual = res['cr0'] + cr_actual = res['cr_a'] print ("CR", cridx, cr_expected, cr_actual) self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code)) diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py index b16e5688..a7291c6c 100644 --- a/src/soc/fu/cr/pipe_data.py +++ b/src/soc/fu/cr/pipe_data.py @@ -10,25 +10,27 @@ from soc.decoder.power_decoder2 import Data class CRInputData(IntegerData): - regspec = [('INT', 'a', '0:63'), # 64 bit range - ('INT', 'b', '0:63'), # 6B bit range + regspec = [('INT', 'ra', '0:63'), # 64 bit range + ('INT', 'rb', '0:63'), # 64 bit range ('CR', 'full_cr', '0:31'), # 32 bit range ('CR', 'cr_a', '0:3'), # 4 bit range ('CR', 'cr_b', '0:3'), # 4 bit range ('CR', 'cr_c', '0:3')] # 4 bit range def __init__(self, pspec): super().__init__(pspec) - self.a = Signal(64, reset_less=True) # RA - self.b = Signal(64, reset_less=True) # RB + self.ra = Signal(64, reset_less=True) # RA + self.rb = Signal(64, reset_less=True) # RB self.full_cr = Signal(32, reset_less=True) # full CR in self.cr_a = Signal(4, reset_less=True) self.cr_b = Signal(4, reset_less=True) self.cr_c = Signal(4, reset_less=True) # needed for CR_OP partial update + # convenience + self.a, self.b = self.ra, self.rb def __iter__(self): yield from super().__iter__() - yield self.a - yield self.b + yield self.ra + yield self.rb yield self.full_cr yield self.cr_a yield self.cr_b @@ -36,8 +38,8 @@ class CRInputData(IntegerData): def eq(self, i): lst = super().eq(i) - return lst + [self.a.eq(i.a), - self.b.eq(i.b), + return lst + [self.ra.eq(i.ra), + self.rb.eq(i.rb), self.full_cr.eq(i.full_cr), self.cr_a.eq(i.cr_a), self.cr_b.eq(i.cr_b), @@ -47,24 +49,26 @@ class CRInputData(IntegerData): class CROutputData(IntegerData): regspec = [('INT', 'o', '0:63'), # 64 bit range ('CR', 'full_cr', '0:31'), # 32 bit range - ('CR', 'cr', '0:3')] # 4 bit range + ('CR', 'cr_a', '0:3')] # 4 bit range def __init__(self, pspec): super().__init__(pspec) self.o = Data(64, name="o") # RA self.full_cr = Data(32, name="full_cr") - self.cr = Data(4, name="cr") + self.cr_a = Data(4, name="cr_a") + # convenience + self.cr = self.cr_a def __iter__(self): yield from super().__iter__() yield self.o yield self.full_cr - yield self.cr + yield self.cr_a def eq(self, i): lst = super().eq(i) return lst + [self.o.eq(i.o), self.full_cr.eq(i.full_cr), - self.cr.eq(i.cr)] + self.cr_a.eq(i.cr_a)] class CRPipeSpec(CommonPipeSpec): diff --git a/src/soc/fu/ldst/pipe_data.py b/src/soc/fu/ldst/pipe_data.py index 85b56f55..089e6014 100644 --- a/src/soc/fu/ldst/pipe_data.py +++ b/src/soc/fu/ldst/pipe_data.py @@ -6,56 +6,60 @@ from soc.decoder.power_decoder2 import Data class LDSTInputData(IntegerData): - regspec = [('INT', 'a', '0:63'), - ('INT', 'b', '0:63'), - ('INT', 'c', '0:63'), + regspec = [('INT', 'ra', '0:63'), + ('INT', 'rb', '0:63'), + ('INT', 'rc', '0:63'), ('XER', 'xer_so', '32')] ] def __init__(self, pspec): super().__init__(pspec) - self.a = Signal(64, reset_less=True) # RA - self.b = Signal(64, reset_less=True) # RB/immediate - self.c = Signal(64, reset_less=True) # RC + self.ra = Signal(64, reset_less=True) # RA + self.rb = Signal(64, reset_less=True) # RB/immediate + self.rc = Signal(64, reset_less=True) # RC self.xer_so = Signal(reset_less=True) # XER bit 32: SO + # convenience + self.rs = self.rc def __iter__(self): yield from super().__iter__() - yield self.a - yield self.b - yield self.c + yield self.ra + yield self.rb + yield self.rc yield self.xer_so def eq(self, i): lst = super().eq(i) - return lst + [self.a.eq(i.a), self.b.eq(i.b), self.c.eq(i.c), + return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb), self.rc.eq(i.rc), self.xer_so.eq(i.xer_so)] class LDSTOutputData(IntegerData): regspec = [('INT', 'o', '0:63'), - ('INT', 'ea', '0:63'), - ('CR', 'cr0', '0:3'), + ('INT', 'o1', '0:63'), + ('CR', 'cr_a', '0:3'), ('XER', 'xer_so', '32')] def __init__(self, pspec): super().__init__(pspec) self.o = Data(64, name="stage_o") - self.ea = Data(64, name="ea") - self.cr0 = Data(4, name="cr0") + self.o1 = Data(64, name="o1") + self.cr_a = Data(4, name="cr_a") self.xer_so = Data(1, name="xer_so") + # convenience + self.cr0, self.ea = self.cr_a, self.o1 def __iter__(self): yield from super().__iter__() yield self.o - yield self.ea + yield self.o1 yield self.xer_ca - yield self.cr0 + yield self.cr_a yield self.xer_so def eq(self, i): lst = super().eq(i) return lst + [self.o.eq(i.o), - self.ea.eq(i.ea), - self.cr0.eq(i.cr0), + self.o1.eq(i.o1), + self.cr_a.eq(i.cr_a), self.xer_so.eq(i.xer_so)] diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py index ba24ce6d..6512324d 100644 --- a/src/soc/fu/logical/pipe_data.py +++ b/src/soc/fu/logical/pipe_data.py @@ -7,47 +7,51 @@ from soc.fu.logical.logical_input_record import CompLogicalOpSubset class LogicalInputData(IntegerData): - regspec = [('INT', 'a', '0:63'), - ('INT', 'b', '0:63'), + regspec = [('INT', 'ra', '0:63'), + ('INT', 'rb', '0:63'), ] def __init__(self, pspec): super().__init__(pspec) - self.a = Signal(64, reset_less=True) # RA - self.b = Signal(64, reset_less=True) # RB/immediate + self.ra = Signal(64, reset_less=True) # RA + self.rb = Signal(64, reset_less=True) # RB/immediate + # convenience + self.a, self.b = self.ra, self.rb def __iter__(self): yield from super().__iter__() - yield self.a - yield self.b + yield self.ra + yield self.rb def eq(self, i): lst = super().eq(i) - return lst + [self.a.eq(i.a), self.b.eq(i.b), + return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb), ] class LogicalOutputData(IntegerData): regspec = [('INT', 'o', '0:63'), - ('CR', 'cr0', '0:3'), + ('CR', 'cr_a', '0:3'), ('XER', 'xer_ca', '34,45'), ] def __init__(self, pspec): super().__init__(pspec) self.o = Data(64, name="stage_o") # RT - self.cr0 = Data(4, name="cr0") + self.cr_a = Data(4, name="cr_a") self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32 + # convenience + self.cr0 = self.cr_a def __iter__(self): yield from super().__iter__() yield self.o yield self.xer_ca - yield self.cr0 + yield self.cr_a def eq(self, i): lst = super().eq(i) return lst + [self.o.eq(i.o), self.xer_ca.eq(i.xer_ca), - self.cr0.eq(i.cr0), + self.cr_a.eq(i.cr_a), ] diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py index 5c34a692..46d383a0 100644 --- a/src/soc/fu/shift_rot/pipe_data.py +++ b/src/soc/fu/shift_rot/pipe_data.py @@ -8,27 +8,29 @@ from nmutil.dynamicpipe import SimpleHandshakeRedir class ShiftRotInputData(IntegerData): - regspec = [('INT', 'a', '0:63'), + regspec = [('INT', 'ra', '0:63'), ('INT', 'rb', '0:63'), - ('INT', 'rs', '0:63'), + ('INT', 'rc', '0:63'), ('XER', 'xer_ca', '34,45')] def __init__(self, pspec): super().__init__(pspec) - self.a = Signal(64, reset_less=True) # RA - self.rb = Signal(64, reset_less=True) # RB/immediate - self.rs = Signal(64, reset_less=True) # RS + self.ra = Signal(64, reset_less=True) # RA + self.rb = Signal(64, reset_less=True) # RB + self.rc = Signal(64, reset_less=True) # RS self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32 + # convenience + self.a, self.rs = self.ra, self.rc def __iter__(self): yield from super().__iter__() - yield self.a + yield self.ra yield self.rb - yield self.rs + yield self.rc yield self.xer_ca def eq(self, i): lst = super().eq(i) - return lst + [self.rs.eq(i.rs), self.a.eq(i.a), + return lst + [self.rc.eq(i.rc), self.ra.eq(i.ra), self.rb.eq(i.rb), self.xer_ca.eq(i.xer_ca) ] diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py index b3ea9879..8b4e343a 100644 --- a/src/soc/fu/trap/pipe_data.py +++ b/src/soc/fu/trap/pipe_data.py @@ -7,59 +7,63 @@ from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace class TrapInputData(IntegerData): - regspec = [('INT', 'a', '0:63'), - ('INT', 'b', '0:63'), - ('FAST', 'srr0', '0:63'), - ('PC', 'cia', '0:63'), - ('MSR', 'msr', '0:63')] + regspec = [('INT', 'ra', '0:63'), + ('INT', 'rb', '0:63'), + ('FAST', 'spr1', '0:63'), + ('FAST', 'cia', '0:63'), + ('FAST', 'msr', '0:63')] def __init__(self, pspec): super().__init__(pspec) - self.a = Signal(64, reset_less=True) # RA - self.b = Signal(64, reset_less=True) # RB/immediate - self.srr0 = Data(64, name="srr0") # SRR0 + self.ra = Signal(64, reset_less=True) # RA + self.rb = Signal(64, reset_less=True) # RB/immediate + self.spr1 = Data(64, name="spr1") # SRR0 self.cia = Signal(64, reset_less=True) # Program counter self.msr = Signal(64, reset_less=True) # MSR + # convenience + self.srr0, self.a, self.b = self.spr1, self.ra, self.rb def __iter__(self): yield from super().__iter__() - yield self.a - yield self.b - yield self.srr0 + yield self.ra + yield self.rb + yield self.spr1 yield self.cia yield self.msr def eq(self, i): lst = super().eq(i) - return lst + [self.a.eq(i.a), self.b.eq(i.b), self.srr0.eq(i.srr0), + return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb), self.spr1.eq(i.spr1), self.cia.eq(i.cia), self.msr.eq(i.msr)] class TrapOutputData(IntegerData): regspec = [('INT', 'o', '0:63'), - ('SPR', 'srr0', '0:63'), - ('SPR', 'srr1', '0:63'), - ('PC', 'nia', '0:63'), - ('MSR', 'msr', '0:63')] + ('FAST', 'spr1', '0:63'), + ('FAST', 'spr2', '0:63'), + ('FAST', 'nia', '0:63'), + ('FAST', 'msr', '0:63')] def __init__(self, pspec): super().__init__(pspec) self.o = Data(64, name="o") # RA - self.srr0 = Data(64, name="srr0") # SRR0 SPR - self.srr1 = Data(64, name="srr1") # SRR1 SPR + self.spr1 = Data(64, name="spr1") # SRR0 SPR + self.spr2 = Data(64, name="spr2") # SRR1 SPR self.nia = Data(64, name="nia") # NIA (Next PC) self.msr = Data(64, name="msr") # MSR + # convenience + self.srr0, self.srr1 = self.spr1, self.spr2 def __iter__(self): yield from super().__iter__() yield self.o yield self.nia yield self.msr - yield self.srr0 - yield self.srr1 + yield self.spr1 + yield self.spr2 def eq(self, i): lst = super().eq(i) return lst + [ self.o.eq(i.o), self.nia.eq(i.nia), self.msr.eq(i.msr), - self.srr0.eq(i.srr0), self.srr1.eq(i.srr1)] + self.spr1.eq(i.spr1), self.spr2.eq(i.spr2)] # TODO: replace CompALUOpSubset with CompTrapOpSubset