From: Bas Nieuwenhuizen Date: Sun, 14 Jan 2018 01:46:49 +0000 (+0100) Subject: radv: Merge vtx_reuse_depth computation with PM4 generation. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e2bf18030d9793dd9586315763d1cf444d0462a3;p=mesa.git radv: Merge vtx_reuse_depth computation with PM4 generation. Reviewed-by: Dave Airlie Reviewed-by: Samuel Pitoiset --- diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 32c381bc49a..3862625e198 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2860,8 +2860,13 @@ radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs, if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10) return; + unsigned vtx_reuse_depth = 30; + if (radv_pipeline_has_tess(pipeline) && + radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) { + vtx_reuse_depth = 14; + } radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, - pipeline->graphics.vtx_reuse_depth); + S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth)); } static void @@ -3178,12 +3183,6 @@ radv_pipeline_init(struct radv_pipeline *pipeline, pipeline->graphics.vtx_emit_num = 2; } - pipeline->graphics.vtx_reuse_depth = 30; - if (radv_pipeline_has_tess(pipeline) && - radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) { - pipeline->graphics.vtx_reuse_depth = 14; - } - if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) { radv_dump_pipeline_stats(device, pipeline); } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index e7b90458d19..d836c95aefe 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1246,7 +1246,6 @@ struct radv_pipeline { bool ia_switch_on_eoi; bool partial_vs_wave; uint8_t vtx_emit_num; - uint32_t vtx_reuse_depth; struct radv_prim_vertex_count prim_vertex_count; bool can_use_guardband; uint32_t pa_sc_cliprect_rule;