From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Fri, 8 Aug 2014 00:27:13 +0000 (-0700)
Subject: Support uarch counters (degenerately)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e2c0c3021ac2fa7cad5866e0f100c2dbf2372986;p=riscv-isa-sim.git

Support uarch counters (degenerately)
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 8ba87ed..4b282f6 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -353,6 +353,23 @@ reg_t processor_t::get_pcr(int which)
     case CSR_FROMHOST:
       sim->get_htif()->tick(); // not necessary, but faster
       return state.fromhost;
+    case CSR_UARCH0:
+    case CSR_UARCH1:
+    case CSR_UARCH2:
+    case CSR_UARCH3:
+    case CSR_UARCH4:
+    case CSR_UARCH5:
+    case CSR_UARCH6:
+    case CSR_UARCH7:
+    case CSR_UARCH8:
+    case CSR_UARCH9:
+    case CSR_UARCH10:
+    case CSR_UARCH11:
+    case CSR_UARCH12:
+    case CSR_UARCH13:
+    case CSR_UARCH14:
+    case CSR_UARCH15:
+      return 0;
   }
   throw trap_illegal_instruction();
 }